Quote Originally Posted by 003 View Post
I could have sworn reading a news article on this. I believe it was from BSN.

Ah, yup I am right. Here is the article in question. Some interesting quotes:

So yes it looks like the current numbers of 520 and 630GFlops are in fact based on A2 silicon, and A3 should up this considerably, as even Charlie admits in one of his latest editorials ("A3 will almost assuredly up the clocks quite a bit...").





2-bit ECC is necessary for high precision HPC applications (i.e. medical imaging). ATI only has 1-bit ECC on the video memory, which isn't enough. Nvidia has 2-bit ECC on the video memory and the entire cache hiercharchy.



I am not the signer of the NDA, I know someone who is and NDA was broken when they talked to me. I will reveal general information that can't be traced back to the NDA signer. Whether or not you choose to believe me is out of my control. Irrelevant though as it will be revealed to everybody in Q1.
No ATI does not have 1bit ECC, it has a EDC based based on parity bit most likely. The ECC also use's EDC BTW there are two stages in how ECC works it detects then it try's to fix the error.

But if unsuccessful it requests the data again, EDC "In ATi's case" always requests the data again it does not try and fix the error. In a case where the error can not be fixed and timeout occurs EDC will be faster than ECC.

The only two things that fermi really has are a very flexable design, programmers can make it flip waffles and the fermi has a very nice FP64 FMA execution system...