Quote Originally Posted by informal View Post
SSE will be serviced directly from shared L2 cache over double width L2 bus(when compared to today's 128b L2).The possible L1 bottleneck would be alleviated this way since FP/SSE stuff would be serviced over another bus from 2nd level shared cache ,leaving L1I and L1D for two 2-way int clusters exclusively .
Yes, but more bandwidth doesn't mean automatically that the cache has a lower latency. AMDs 1st level cache where always superrior in terms of latency to intels 1st level cache, but they lacked in the 2nd level department.