AMD Analyst Day. No 32nm products til 2011.

[informal]

Editied original post, again first impression was -> wth looks like dunnington (cache wise). I corrected that.
The core has an interesstening concept, but no 1st levle cache for FP seems quite risky, if the 2nd level cache isn't fast enough.

SSE will be serviced directly from shared L2 cache over double width L2 bus(when compared to today's 128b L2).The possible L1 bottleneck would be alleviated this way since FP/SSE stuff would be serviced over another bus from 2nd level shared cache ,leaving L1I and L1D for two 2-way int clusters exclusively .