AMD Analyst Day. No 32nm products til 2011.

[Hornet331]

Dunno,why?In what regard? It doesn't remind me of dunnington at all
The design approach like this has never been tried before(shared front end with hardware mutithreding based on sharing some parts of the core,namely integer execution units,while having SMT like FPU/SIMD which will be dual thread capable a la SMT and 256b wide;shared L1I cache among int clusters,globally shared L2 and L3;AVX support ;advanced turbo clock/boost features for individual parts within a "core" etc.).
Dunningtion is basically monolithic design based on 3 merged Penryn dice with huge L3 to alleviate the FSB bottleneck(which is still there...).Nothing novel uarchitecture wise.

The BD design approach has only been discussed in several academic papers thus far,and in Fred Weber's (AMD) presentation from 2005. No company has ever made a MPU based on this multithread design.It's a risky move but they seem pretty confident in the abilities of the new core.

Editied original post, again first impression was -> wth looks like dunnington (cache wise). I corrected that.
The core has an interesstening concept, but no 1st levle cache for FP seems quite risky, if the 2nd level cache isn't fast enough.

Similar to dunnington?? Are you serious??

do you even read any post beyoned the first sentence?

[informal]

Editied original post, again first impression was -> wth looks like dunnington (cache wise). I corrected that.
The core has an interesstening concept, but no 1st levle cache for FP seems quite risky, if the 2nd level cache isn't fast enough.

SSE will be serviced directly from shared L2 cache over double width L2 bus(when compared to today's 128b L2).The possible L1 bottleneck would be alleviated this way since FP/SSE stuff would be serviced over another bus from 2nd level shared cache ,leaving L1I and L1D for two 2-way int clusters exclusively .

[Hornet331]

SSE will be serviced directly from shared L2 cache over double width L2 bus(when compared to today's 128b L2).The possible L1 bottleneck would be alleviated this way since FP/SSE stuff would be serviced over another bus from 2nd level shared cache ,leaving L1I and L1D for two 2-way int clusters exclusively .

Yes, but more bandwidth doesn't mean automatically that the cache has a lower latency. AMDs 1st level cache where always superrior in terms of latency to intels 1st level cache, but they lacked in the 2nd level department.

[Face]

Didn't see these two posted yet:

[flippin_waffles]

do you even read any post beyoned the first sentence?


Editied original post, again first impression was -> wth looks like dunnington (cache wise). I corrected that.
The core has an interesstening concept, but no 1st levle cache for FP seems quite risky, if the 2nd level cache isn't fast enough.

Depends who's posting.