Dresdenboys' blog: AMD Bulldozer - Patent based research

[ajaidev]

Just to add, Sun has their UltraSPARC T2 Processor specs HERE. Notice, 8-threads per core, 2 instruction pipelines + 1 floating point unit + 1 stream processing unit (cryptographic). In Dresdenboy's diagram, I see 4 instruction pipelines. Given the differences between SPARC and x86, AMD may very well be getting 4 threads out of a core (welcome to the 21st century, AMD).

If anything, we can at least expect 4 instructions per cycle like Intel's Core 2 and Nehalem, up from K10's 3 .

I think the PowerPC7 tech may have deeper impact on BD than SPARC... It was long rumored that PoerPC7 and Future amd server processors will share the same socket. Also SPARC uses SMT to get the 8 TPC AMD already said they don't like it, i even asked a question on SMT on AMD work the replay was pretty anti SMT to say the least.