AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

You do know that SSE5 is dead by itself and moved into AMDs new spec in the Volume 6 PDF? Right?

And that the instructions in Volume 6 is FAR from the same as Intels AVX spec? Right?

Or is AMD now wrong or is it some later revision of Volume 6 or some new Volume 7 that will back up your claims? You have everything pointing against you with your superset.

AMD seems to choose to support a selection of the AVX instructions. those they have most faith in. However there is no promoted SSE instructions in form of VEX.128 and VEX.256 that is also part of the AVX spec just to mention the most obvious.

Volume 6 IS an SSE5 in AVX form(using VEX decoding) .It IS AMD's special set of instructions,an addition. ADDITION.
AVX support means a support for complete AVX set of instructions,like Mr Christie already confirmed .

I should have mentioned something about these. We intend to support all of it, with the possible exception of CVT16, which might not appear in the initial AVX-compatible products (hence the separate feature flag)

And "these" or "all of it" are these(taken from question Mr Fog directed to Mr. Christie in devblog i already linked to):
* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers