AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

I already linked to one of the designers of very Bulldozer core. You can start eating ... now. Maybe you are a secret member of Bulldzoer design team ? If you are,then you probably know better than Mr. Christie lol

Also a re-post of my previous post :

More information on AVX support in BD cores,directly from senior architect Mr. Christie,as response to Agner Fog's inquiry in comments section of the blog:

AMD deserves praise for this important move towards convergence and compatibility. The changes in the SSE5 spec. have very much followed the lines I have argued heavily for in the AMD developer forum and elsewhere. It is impossible to maintain compatibility when the development cycle is several years and AMD and Intel both keep secrets to each other. It was therefore a very good move when AMD published their proposed SSE5 spec years in advance. A move that Intel responded to by also publishing their AVX proposal in advance. Let's hope this new tradition continues. The whole industry is crying for compatibility. I can certainly imagine your reaction when Intel announced their last minute change from FMA4 to FMA3!

Our worst nightmare would be Intel copying the XOP instructions but making them incompatible with AMD by replacing the XOP prefix by a VEX prefix. I hope you have legal remedies to prevent such a move.

Could you perhaps outline a roadmap for if or when the various instruction sets will be supported by AMD CPUs:

* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers

How much of this will be supported in Bulldozer?

Agner Fog's post at Ace's:

According to Dave Christie, AMD will support all Intel instructions in Bulldozer, including AVX, SSE4.1-2, AES and PCLMULQDQ.
http://forums.amd.com/devblog/blogpo...d=208#comments.

They must have been working very hard to implement all that within such a short timeschedule. I am sure they will implement the 256-bit vector registers as two 128-bit registers, but so will Intel.

So another confirmation of the topic title and another proof shintai was wrong


* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers

I should have mentioned something about these. We intend to support all of it, with the possible exception of CVT16, which might not appear in the initial AVX-compatible products (hence the separate feature flag)