AMD embraces AVX making a new superset with SSE5(256bit support)

[Shintai]

It's not new pdf,ffs man.. It's an old spec. of SSE5 since you said and I quote :"Hence there is NO former SSE5 instructions." There are and i gave you a link. XOP extensions,the one AMD links to are an added(made by AMD ) instructions, that are a sort of "leftover" from SSE5.These weren't duplicated in AVX and since AMD already got a positive review from developers they decided to use VEX decoding scheme on them and include them too(like a new 3dnow if you will). When Mr. Christie(a BD core design team member) stated they will support version 5 of AVX,it means they will support version 5-no mroe no less. You can find version 5 online and guess what-in order to be compatible ,the instruction format must be the same.

You do know that SSE5 is dead by itself and moved into AMDs new spec in the Volume 6 PDF? Right?

Or do I even have to repost your own quotes:

Now, originally we had focused on what we had called SSE5, a specification we proposed for review by the industry in 2007. However, due to the overlap of functionality between the AVX instructions and SSE5, AMD has decided to recast the SSE5 instructions into the AVX framework. AMD made decision to ensure the continued compatibility of x86 software, and plans to incorporate AVX instructions into AMD processors in 2011

And that the instructions in Volume 6 is FAR from the same as Intels AVX spec? Right?

Or is AMD now wrong or is it some later revision of Volume 6 or some new Volume 7 that will back up your claims? You have everything pointing against you with your superset.

AMD seems to choose to support a selection of the AVX instructions. those they have most faith in. However there is no promoted SSE instructions in form of VEX.128 and VEX.256 that is also part of the AVX spec just to mention the most obvious.