AMD embraces AVX making a new superset with SSE5(256bit support)

[informal]

Ahh i give up.You are something special. Your "marketing" claim is garbage since the post is from AMD's architect,not marketing dude.The engineering fellow said they will fully support AVX and add their own extensions(XOP etc.). If you can't understand this ,please try harder. It's simple and straightforward.If you are compatible with AVX it means you support the versions listed at intel's site .The XOP IS an additional extension set as it adds FMA among other stuff. FMA IS NOT in Sandy Bridge. You can read up some comments AMD's partners made about AMD's announcement and those quotes from them clearly state AMD will fully support both AVX and their own XOP instr. sets.

I can only speculate that your gigantic phailure to understand this comes from you inability to admit that you were wrong from the start.Now you keep digging that hole deeper and deeper and you can't get out of it...

PS Again for you from Mr. Christie:

With this duplication of functionality between SSE5 and AVX/FMA, and AVX's additional features, we felt the right thing to do was to support AVX. In our minds, a more unified instruction set is clearly what's best for developers and the x86 software industry. With our acceptance of AVX, a key aspect of this instruction set unification is the stability of the specification. Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

Again,XOP extensions is and add-on,an "extra" if you will,proof is here:

This week, AMD is making a couple of very important announcements for developers: support of Intel's Advanced Vector Extensions (AVX) instruction set in future AMD processors, and the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal. The latter step has resulted in three new extensions: XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add). In this posting I'll give an overview of the capabilities that these extensions provide, and also some insight into why we're taking this step.

As you can see,the paragraphs states in no uncertain terms that there is a full AVX support with an added extra extension that consist of SB' lacking feature named FMA(among other things).AMD's XOP ext. set is a "leftover" from SSE5,the stuff that didn't overlap with AVX but could be a valuable addition to BD cores. Simple as 1-2-3. Keep reading it until you figure it out