I have been experimenting with MEM, an observing some strange results. After long and heavy MEM-testing, loose tRAS seams to play a bigger role (bigger than what we are used to on CD2) for MEM-stability at higher BCLK.

I have been testing with 8 instance av 50MB memtest 3.8, and have made these observations:

@4GHZ(211x19) HT:on:
@1266 7-7-7-20 1.65v fails (same with tRAS 21 to 24). I didn't test higher tRAS.
@1266 6-6-6-18 fails (same with tRAS 19 to 29), but tRAS 30 passes

@3.8GHZ (200x19) HT:on:
@1200 7-7-7-20 1.65v fails, but tRAS 21 passes
@1200 6-6-6-18 1.65v fails (same with tRAS 19 to 23), but tRAS 24 passes

Almost all fails accrued in 60% to 70% during the memtest.

Loose tRAS seams to be play a big role on MEM-stability at higher BCLK (at least on my CPU and RAM) and seams to have some effect on Vcore too. After i got it stabilized @1266 6-6-6-30 1.65v, i could prime "pass the kill zone" with 1.32v @4GZ(211x19) Ht:On, with is "several notch" lower than the previous Vcore requirement (1.34v).

Anybody else has observed similar behavior?