Live MB OC Report :: ASUS Rampage Extreme

[mikeyakame]

dont mind posting just that some joker will take this and make it a permanent guide for everything...
that is just pure misinformation

ok ram skewing guide for e8600 + samsung hco 2x2gb dimm a2/b2 the rest u have u test it ureself

software needed memtest86 / IBT / Orthos

Before u begin u must set the cpu skew/nb skew.. and not leave it in auto.
for e8600 confirmed up to 500fsb both is set at normal
oops forgot to mention that.


CLK Skew
first skew to test would be clk leave the rest in auto
so far i found that leaving Channel A +25 advance more than Channel B
use IBT to confirm say in windows diagnostic mode 4gb kit atleast 60 roughly 4 hours and 2gb kit atleast 200 runs with 1600mhz above i had to use clk skews +nb/dram vtt

CTL Skew and CMD Skew
with the ram i tested i found out that CMD skew is the indicator for ctl skew
meaning if the cmd skew is on delay than the ctl skew also must be in delay
if the cmd skew is on advance than the ctl skew is also in advance
and for me cmd skew is best with channel A1/A2 advance 50 to channel B1/B2
and for ctl skew like cheapseat uses channel A1/A2 delayed 25 to channel B1/B2

Test first initial test
use memtest86 test 5 only and run in loops... set vdimm one notch below than the perfect vdimm confirmed at ure setting
test 5 for memtest86 is the best indicator for nb voltage/vdimm voltage and skewing stability and also tRFC..
so example if u set cmd skew in delay then delay the ctl skews and test
find the limit.
later retest with clk skews to find the best almost perfect to pass excepts maybe hangs on pass 2-3. Take note there is no errors.. only hang.. if errors that means skewing is wrongly set.

Retest with orthos in diagnostic mode
Set to blend.. and then custom min fft 4096 max 4096 priority 10.
try to pass more than 4 hours... take note this is hard.. a lot of test that will pass memtest86/hci memtest will not pass this.
example the config above trfc 60 pass 35 mins/72 4hours 12 mins/88 24 hours manually stopped
also noted was at 563 fsb fsb termination at 1.19 for IBT but for this test requires 1.29
have fun

1600 CL7 tRFC 110.. vdimm 1.65 for samsung hco 2x2gb with the same skewing

then try running 3dmark06 in loops.. and see whether ure gc fps sometiemes goes haywire..
so far with the skewing i did above solved all this issue


eh sorry typo had to give back my rampage 2 extreme.. test unit
and sold off the rampage extreme because i am tired and dont think can go further

also last note.. with the skewing above u can reduce ure nb voltage example for 563 fsb from no skewing at 1.61set(1.59set) to skewing at 1.59set( 1.56 true).. i call that worth it...
so far doesnt do much for vdimm voltages for me personally
also y skewing is so important
so far from my experience if i get 4ghz and whatever fsb super stable and all the skewing right.. then upping the multi and vcore is 100% confirmed and trouble free from any ram or nb voltage issues...this is y this mobo can do 4.5ghz confirm stable everytime
the maximus 2 etc.. i can get today 4.5ghz stable 6 hours small fft priority 10.. and again tommorow fail in 3 minutes.. and next day pass 1 hour etc etc.. because of skewing..
vcore voltage reduction ... cmd skews affects this..

if you are interested in what the bios skew settings actually change, you can look at mchbar register dumps.

the offsets are:

for clock fine delay, value in register equates to: 1h = ~50ps values are in delay clock periods. ie. 1T.
This is the register format as anexample.

At 513h offset = 35h, 5 = Dimm1 (A1) Fine Delay, 3 = Dimm2 (A2) Fine Delay
At 913h offset = 34h, 4 = Dimm3 (B1) Fine Delay, 3 = Dimm4 (B2) Fine Delay

512h offset = 96h, 6 = Channel A Data Strobe Skew (tDQS) DRAM end of cross clocking, 9 = Channel A Data Strobe Delay Skew MCH end of cross clocking
912h is the same, ie 94h.

Since there is no data from Intel on these registers, their definition is what I understand they reflect. DFI's X48 bios allows these values to be set individually so I'm going off the way they name the options, haven't sat down and double checked on a DFI board but as far as I can tell they should be correct. I've changed their values at the registers manually and ran multiple synthetic benchmarks for each change. The change in memory bandwidth with adjustment reflects DFIs definition of what they do.

FED14510-11h 00 00
FED15512-13h 96 35
FED14910-11h 00 00
FED14912-13h 94 34

channel A dimm 1+2 clock fine delay is 14513h, channel A address strobe skew is 14512h.
channel B dimm 3+4 clock fine delay is 14913h, ( 1h = 50ps values are in delay clocks ), channel B address strobe skew is 14912h.

Data Strobe Skews may be in nano seconds or cross clock periods, hard to say.

cpu / nb clock skews set the delay from know clockgen turnaround skew on the ic, to when the cpu and nb drive their internal clock waves and meet necessary time to setup/pulldown/complete bus transactions end to end. if there is a setting to change the differential drive amplitude, increasing it gradually as FSB frequency becomes faster and faster can help to limit excess deskew from taking place and give much finer adjustment with a bit of trial and error. this becomes increasingly critical as the period for a clock becomes smaller as frequency gets higher, 100ps will at times be too coarse to obtain stability or consistency.