Quote Originally Posted by mikeyakame View Post
just keep vtt under 0.3v above vcc and you wont have a problem. once u increase potential across cpu landing pin input voltages u gradually begin to risk stressing the silicon as it tries to cope with constant differences between vcc and vtt which is used for input buffer threshold on low/high swings.
For clarification, that 0.3v isn't a typo for 0.03v right? I've got vcore at 1.45v (Windows: 1.42v idle, 1.41v load) and VTT at 1.54.