New Memory Tweaker for Intel Chipsets

[DualCpuUser]

Felix, two things... 1) Please rename your cpu-tweaker for i7... I vote for i7-Tweaker, and leave your Cpu-Tweaker same for all others. That way I not mix them up and execute the wrong one, as I just did!

I look in this thread for the < i7 tweaker and monitor this thread for your updates to the non i7 version.

[FELIX]

...Why do you want that I rename it? CPU-Tweaker work on both CPU Core i7 and Phenom. Memset work on others.

MemSet 3.6

-Fix a bug with EPP abreviated profile detection.
-Add support for Intel Q45/G41 chipsets.
-Add support for Intel G35 chipsets.
-Add support for Intel PM45/GM45 (Mobile) chipsets.
-Add support for NVidia NForce 630i & 790i FTW chipsets.
-Fix a bug with the Save function on Intel chipsets.
-Improve reading frequency with some Intel CPU.
-K10 support has been removed in this version (Use CPU-Tweaker now).

CPU-Tweaker 1.0 beta4

Only for Processor with Integrated Memory Controller:
-AMD Phenom DDR2 & DDR3.
-INTEL Core i7 DDR3. (Timings and frequency Reading only)

[gymenii]

-Improve reading frequency with some Intel CPU.

merci!

[Monstru]

Great work Felix, especially the CPU Tweaker is a very handy tool, now I can test RAM on nehalem with more ease. Everything going ok untill now.

[BenchZowner]

Great work Felix, especially the CPU Tweaker is a very handy tool, now I can test RAM on nehalem with more ease. Everything going ok untill now.

I don't think you paid enough attention to Felix's post mate.
The CPU Tweaker CAN'T change the memory timings on the LGA1366 platform yet.

[Monstru]

I didn't had time to test before I post this, bad luck

[mikeyakame]

Felix

Just curious in which manner you are using to write the pci registers?
I think I read that you are using a ring0 driver, so if thats the case you are attempting to write the NHM pci registers while at priv level 0.

Ie. transitition from priv 3 to 0 and then back to 3 by SYSENTER/SYSEXIT instructions right? The pci registers are definitely RW flagged not RWO. If you are using WRMSR to mov the ESP, EIP, CS data to their corresponding msr offset address, then making a SYSCALL or SYSENTER, and then executing the instructions pointed to by IA32_SYSENTER_EIP msr you wrote before making the call.

If that is along the lines of the method you are using and its not working, I'm wondering if it is possible to switch to real-address mode without causing a GP exception and manually set the registers bits if its possible to use the pci offset:address in real-address mode that is. If the PCIBAR isn't locked which it shouldn't be since it's used for counters and such too, and the bios can change its values I'm thinking it may not be that it can't be done, but rather the precursors for doing it. I've read briefly through the I7 datasheets and from what I understand that there are rules setup for access control to certain address ranges and registers. If you hadn't come across this it, my understanding is on different bus interconnects there are different access rights for say pcie, qpi, dmi, smbus, etc based calls depending on what the devices on that end need priviledge to do. If the origin of the call is say QPI bus, then there are rules setup to restrict access when reading and or writing certain hw address registers or memory offset locations.

I may be understanding that wrong, but if i'm not then a theory I have is if this was true, what if a roundabout method was used to write rule restricted registers by forwarding the call as such through a bus that matches the access control to write that register, since it checks source flag to match access it might be another means which the bios does it, since Intel would have let all the bios engineers know exactly how to write the registers if protected in such a way that opening them up for write access could mean that if you write one RW reg it may be possible to change any that arent RWO or RO. This just came to mind, and thought it was worth sharing. If I come up with anything more that's worth mentioning I'll pass it over.

Intel engineers would have put in place more than 1 method of writing pci registers since we know the bios can do it and the rules for the bios doing it should be no different than your app doing it, just a matter of exposing the means if its not documented.

[vld]

why is there no performance level changer for pm45 ?



why is there no performance level changer for pm45 ?

[GrossmeisterB]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

[BenchZowner]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

It's been said a few times already.
Chipset limitation.

[Ace-a-Rue]

Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??

if you mean memory tweaker can not change it, you are not alone...in order to make a change to CAS, the puter normally has to shutdown to effect the change or at least have a restart after making the change from the bios.

[pangingIII]

Felix,

the Intel P45 chipset's stepping report on Memset version 3.6 is seems to be wrong on one motherboard model at least.

2 of my Gigabyte EP45-UD3R's... in Memset 3.5.8 and CPU-Z, Everest, the chipset stepping is reported as an A3 step.
and starting from Memset 3.5.9 (and 3.6 final) the program reports as an A2 step (CPU-Z, Everest still reading and reporting as A3 step)
i'm just curious and wondering if you can check and advise me on this.

[FELIX]

-> mikeyakame: simply registers are locked by a bit (probably RWO) on Core i7, comfirmed by Franck.

-> vld: I don't know where is localized Performance level registers on mobile chipsets. I can't do nothing.

-> pangingIII: as you can see in this datasheet at page 8, P45 stepping is A2, but I can make a mistake.

[zalophus]

Currently have 3.4 installed, which has been working fine.

I installed 3.6, and it opens with "mchbar" in locked position, and I have found no way to unlock it, meaning I can't adjust any of the settings or expand to see both modules.

I'm ok with 3.4, but am curious if anyone has idea(s) about why this is happening.

[vld]

-> vld: I don't know where is localized Performance level registers on mobile chipsets. I can't do nothing.

Well then there is like no use for memset Please try your best to find out where the performance level registers are on the p45 mobile chipset. If you need any help ask me and I can provide some info.

[Fitseries3]

on rampage 2 extreme (x58) i cant change any values in cpu-tweaker. whats up with that? it wont let me apply or save.

[BenchZowner]

on rampage 2 extreme (x58) i cant change any values in cpu-tweaker. whats up with that? it wont let me apply or save.

Read the previous page m8.
It's just 10 posts away from you.
Currently FELIX doesn't have the necessary resources to make it work ( can't write new values ) on the i7 platform.
It's in read-only mode for the time being.

[mikeyakame]

Felix.

On I7 check PCI Bus DID 0x2C01h offset 0x4Ch. Register SAD_SMRAM[12] = 1, SAD_SMRAM[14] = 0. SAD_SMRAM[12] should be RO if set to 1, SAD_SMRAM[14] should be RO if set to 0.

[FELIX]

I already read this passage from the doc,
but I don't know what it means SMM (in the docs) and if it addresses a memory space or PCI bus.

[FELIX]

New memset version: MemSet 4.0 beta 1

-Use WinRing0 driver instead TVicPort.
-Interface is the same for all chipsets/CPUs.
-Add support for Intel Core i7 CPU (Reading only).
-Loading time was improved.

[gymenii]

Thanks, well done

[msgclb]

I have one problem with the new MemSet 4.0 beta1 and that is it shows my memory as DDR3 0.0 MHz. Tell me that I'm not the only one having this problem.

[ol'norton]

It also disagrees with CPU Tweaker on some of the settings.

[mikeyakame]

ol norton,
looks like felix has subtracted the 2T extra that cpu tweaker is reading that the bios doesn't.

felix,
pretty sure its pci as i remember it saying you address SAD by device id on pci bus, addressing devices 4-6 for memory channels would be the same method no?

[Goldenatom]

New memset version: MemSet 4.0 beta 1

-Use WinRing0 driver instead TVicPort.
-Interface is the same for all chipsets/CPUs.
-Add support for Intel Core i7 CPU (Reading only).
-Loading time was improved.

Super impressed with the speed at which this is moving along. Thanks for the work.