Well, It's not from IBM . It's a paper from the AMD Dresden guys who did
manage to do this. I presume they use the (more or less) standard
reference point of 1V/100nA/um. IBM tends to use 200nA/um
Yes, The very high PMOS current is because of their gate replacement
process. By etching the whole polysilicon gate away they leave a big gap
and all the strain is released on the channel.
Intel's 32nm HKMG numbers are: Intel is 1550/1210 at 1V and 100nA/um Ioff.
http://btbmarketing.com/iedm/release...news_final.doc
There are also some HKMG numbers from IBM/Freescale/AMD
1630μA/µm and 1190μA/µm have been demonstrated at 1V and 200nA/μm off
corrected for 100nA that would be 1570/1160μA/µm or so.
http://www.his.com/~iedm/program/sessions/s27.html
All still R&D papers of course at the moment.
Regards, Hans






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