ASUS Maximus II Formula - new P45 king?

[Grnfinger]

Nice, wish I could get a Template for a starting point for 500FSB, I crash after a while with what I have tried so far.

I know there is a lot of settings I ain't changed as I don't understand them all yet (coming from AMD then Intel on NF Chipsets).

Any help would be welcome.

PLL and NB volts will be key to higher FSB
I have an 8600 @ 555FSB someplace, let me look for it and I'll post it up shortly

Ai Overclock Tuner: Manual
Ratio CMOS Setting: 8
FSB Frequency: 555
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: Auto
DRAM Frequency: DDR2-1112MHz
Dram Clock Skew CH1 A1 : Advanced 300ps
DRAM Clock Skew CH1 A2 : Normal
Dram Clock Skew CH1 B1 : Advanced 300ps
Dram Clock Skew CH1 B2 : Normal

DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 55
Write Recovery Time : 6
Read to Precharge Time : 3

Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6

Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 5
ALL PRE to REF Delay : 5

DRAM Static Read Control: Enabled
Dram Read Training : Enabled
MEM OC Charger : Disabled
Ai Clock Twister : Stronger
Transaction Booster : Manual
Common Performance Level [8]

Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled

PCIE Frequency : 101

CPU Voltage: 1.41875
CPU PLL Voltage: 1.61925 ( yes I know it high but its what got the chip stable)
FSB Termination Voltage: 1.24575
DRAM Voltage: 1.93250
North Bridge Voltage: 1.28550
South Bridge 1.5 Voltage: Auto
South Bridge 1.1 Voltage: Auto

CPU GTL Reference (0): Auto
CPU GTL Reference (1): +40mv
CPU GTL Reference (2): Auto
CPU GTL Reference (3): +40mv
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto