I find this board very frustrating to work with be it with 0501,0601 or my present 0701.

Would really like some advice with the QX9650 + Mushkin 996625. Watercooled, temps idle 26,27,25,30 using Realtemp. Stable 280x8. As soon as I try x9 OCCT reports voltage instability but more importantly, Prime blend or smallf will not pass. I've tried a number voltage combinations, even max most of the voltages to just before yellow indications and no go. Greg was very helpful at Mushin but I think that I need a second or third opinion.

Extreme Tweaker
Ai Overclock Tuner: Manual
OC From Memory Level Up: Auto
FSB Frequency: 480
CPU Ratio Setting: 8
CPU Configuration
C1E Support: Disabled
CPU TM Function: Disabled
Max CPUID Value Limit: Disabled
Vanderpool Technology: Enabled
Execute Disable Bit: Enabled
Core Multi-Processing: Enabled

CPU Clock Skew: Auto
NB Clock Skew: Auto
FSB Strap to North Bridge: AUTO
PCIE Frequency: 100
DRAM Frequency: 1601Mhz
DRAM Command Rate: 1N
DRAM Timing Control: Manual
1st Information: 7-7-6-18-8-88-8-9
CAS# Latency: 7
RAS# to CAS# Delay: 7
RAS# Pre Time: 6
RAS# ACT Time: 18
RAS# To RAS# Delay: 8
REF Cycle Time: 88
WRITE Recovery Time: 8
READ to Pre Time: 6
2nd Information : 10-6-7-5-7-5-7
READ to WRITE Delay (S/D): 10
WRITE to READ Delay (S): 6
WRITE to READ Delay (D): 7
READ to READ (S): 5
READ to READ (D): 7
WRITE to WRITE (S): 5
WRITE to WRITE (D): 7
3RD Information: 24-8-1-10-10
WRITE to PRE Delay: 21
READ to PRE Delay: 8
PRE to PRE Delay: 1
ALL PRE to ACT Delay: 10
ALL PRE to REF Delay: 10
DRAM Static Read Control: disabled
DRAM Dynamic Write Control: disabled
DRAM Skew Control

DRAM CMD Skew on Channel A: Auto
DRAM CLK Skew on DIMM A1: Auto
DRAM CLK Skew on DIMM A2: Auto
DRAM CTL Skew on DIMM A1: Auto
DRAM CTL Skew on DIMM A2: Auto
DRAM CMD Skew on Channel B: Auto
DRAM CLK Skew on DIMM B1: Auto
DRAM CLK Skew on DIMM B2: Auto
DRAM CTL Skew on DIMM B1: Auto
DRAM CTL Skew on DIMM B2: Auto


Ai Clock Twister: Lighter
Ai Transaction Booster: Manual

Common Performance Level: 08
Pull-In of CHA PH1: Disabled
Pull-In of CHA PH2: Disabled
Pull-In of CHA PH3: Disabled
Pull-In of CHB PH1: Disabled
Pull-In of CHB PH2: Disabled
Pull-In of CHB PH3: Disabled

EPU II Phase Control: Auto
CPU Voltage: 1.41
Load-Line Calibration: Disabled
CPU PLL Voltage: 1.53756
FSB Termination Voltage: 1.325
CPU GTLVerf (0): +50mv
CPU GTLVerf (1): +50mv
CPU GTLVerf (2): +50mv
CPU GTLVerf (3): +50mv
NB GTLVerf: +60mV
North Bridge Voltage: 1.60372
DRAM Voltage: 1.90856
NB DDRVref: +37.55mv
DDR3 ChannelA Vref: +12.5mv
DDR3 ChannelB Vref: +12.5mv
South Bridge 1.5 Voltage: 1.51106
South Bridge 1.05 Voltage: 1.06039
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled


I've tried several skew combination between 25/50 to 50/100.