Quote Originally Posted by savantu View Post
Weren't people saying that cache size is all that matters ?
LOL, yeah. Now what is it really?
According to JJ it's (also) due to branch prediction improvements. As Superpi is just a huge loop IIRC.

Quote Originally Posted by Bellisimo View Post
12.7 is really slow for 4ghz
triple channel DDR3, really fast l2 and 8mb of fast L3 might help....
I'm pretty sure the memory speed is important for 16 and 32M. I'm not sure about 1M, though.

EDIT:
Quote Originally Posted by informal View Post
T-Flight if you believe intel chips and chipsets have no "bugs",you should check the current errata list...

PS Intel had a "TLB" issue too,even before Barcelona launched,but they reacted fast too :
http://www.theinquirer.net/en/inquir...e-2-cpu-errata
http://www.dailytech.com/Intel+Expla...ticle10362.htm
Maybe he meant Intel doesn't do showstopper bugs?