X48 Rampage Formula Preview.

[mikeyakame]

How do you understand from above data that you have correctly setup the enabled/disabled phase data for your configuration?

Actually I am at FSB 450, strap 333, divider 5/6, performance level 8 and every phase on ENABLED. I have DRAM skew put to ADVANCED 250 ps both channels as if I follow your suggestion to put A 50 ps delay and B 300 ps advance, I have big instability.

Following your test and guess, I may change to DISABLED some phases....can I understand which one from above Everest values?

With skews easiest way to see which settings work and which don't is by using Test #5 in memtest86+ find settings which give you minor errors and adjust skews to see whether the errors occur earlier or later. Just try leaving Channel B on normal, and delaying Channel A bit by bit and see if its any more or less stable. Takes time, skews only really help at much higher DRAM frequency. I don't really need to skew CHB much until I push past 1160mhz. I run CHA with delay of 250PS atm, and CHB on auto at 1150 5-5-5-15 and 2.3v.

Also from everest, you can tell I've pulled in the last 1 or 2 phases from Read Delay Phase Adjust. The Dimm Fine clock adjust means i've pulled in or pulled out The first 2-3 phases (depending on divider). For 5:6 divider I would try Pull in A1 / A4 / A5 /B1 / B4 / B5. A1 / B1 first, then others. A4 / B4 / A5 / B5 should alter Read delay phase adjust. Others should alter Dimm Clock Fine Adjust. Im 90% PH4 alters it, but I know PH5 definitely does.

In everest cache benchmark i get ~ 52.8ns / 0.9ns / 3.5ns. This ram struggles to push much lower latency than that. Lowest I've gotten was around 51.2ns / 0.7ns / 3.4ns at 490fsb

Note that skews aren't constant values, they change as DRAM frequency changes. Trace lengths are relative to the clocking frequency.