ATI Radeon HD 4000 Series discussion

[Seraphiel]

I can't quite understand how the rumoured texture buffer sharing for the dual die solution would work. Any PCIe-based bridge chip would choke on the bandwidth involved with GDDR5. How would it work?

I puzzled by this as well.

Perhaps the ring bus is part of the solution, and the bridge chip is also part of some MCM package (2 dies + bridge chip + pershaps even an external memory controller). Perhaps the bridge chip isn't needed at all, if it is a MCM package with a little design change because of shared socket.

Pure speculation of course. I don't know or have any idea, because it shouldn't be a simple solution, at least not with the way stuff works now or is designed.