ATI Radeon HD 4000 Series discussion

[largon]

I can't quite understand how the rumoured texture buffer sharing for the dual die solution would work. Any PCIe-based bridge chip would choke on the bandwidth involved with GDDR5. How would it work?


bhavv,
That's nice. Now begone before you go on any further.
As far as I know I haven't recommended anyone to buy or not to buy anything or trashed ATi in any way here.

[Mungri]

bhavv,
That's nice. Now begone before you go on any further.
As far as I know I haven't recommended anyone to buy or not to buy anything or trashed ATi in any way here.

As far as I know I was talking to someone else that said ATI drivers are worse then Nvidia on the previous page, then you come out of nowhere and start misquoting and misreading what I said.

As far as I know I haven't recommended anyone to buy or not to buy anything or trashed ATi in any way here.

[Seraphiel]

I can't quite understand how the rumoured texture buffer sharing for the dual die solution would work. Any PCIe-based bridge chip would choke on the bandwidth involved with GDDR5. How would it work?

I puzzled by this as well.

Perhaps the ring bus is part of the solution, and the bridge chip is also part of some MCM package (2 dies + bridge chip + pershaps even an external memory controller). Perhaps the bridge chip isn't needed at all, if it is a MCM package with a little design change because of shared socket.

Pure speculation of course. I don't know or have any idea, because it shouldn't be a simple solution, at least not with the way stuff works now or is designed.

[AliG]

I puzzled by this as well.

Perhaps the ring bus is part of the solution, and the bridge chip is also part of some MCM package (2 dies + bridge chip + pershaps even an external memory controller). Perhaps the bridge chip isn't needed at all, if it is a MCM package with a little design change because of shared socket.

Pure speculation of course. I don't know or have any idea, because it shouldn't be a simple solution, at least not with the way stuff works now or is designed.

Thing is though, I think this is designed to be an mcm, not just two gpus on a single board, I don't think there will need to be an external bridge chip. Think about it, if they have a shared ringbus, then that means this is more than just two rv770s in a dual die mcm, there has to be some modifications to basically meld the chips to be detected as one thus eliminating the need for a bridge chip. That's probably the whole point of doing this rather than the 3870x2 design.

Man I just wish we'd finally get some legit info already, or if we have, that ati would confirm it

[Seraphiel]

Thing is though, I think this is designed to be an mcm, not just two gpus on a single board, I don't think there will need to be an external bridge chip. Think about it, if they have a shared ringbus, then that means this is more than just two rv770s in a dual die mcm, there has to be some modifications to basically meld the chips to be detected as one thus eliminating the need for a bridge chip. That's probably the whole point of doing this rather than the 3870x2 design.

Man I just wish we'd finally get some legit info already, or if we have, that ati would confirm it

I totally agree

It really sounds promising and I rather be an optimist than a pessimist. This could be the advantage NVIDIA can't break until after its nextgen (GT-200(?)). I hope so, because NVIDIA needs a little humility... This said as a user that has spend >4500$ on NVIDIA product in the last 18 months.

Humility benefits everyone.