Quote Originally Posted by justapost View Post
Still figuring out how the ref HT is generated out of all those settings. The board is not limited to 280MHz.
According to that data, only HT to 280MHz is defined for the SB600 PLLs with X2s. They don't have data for K10 in there, the new docs are supposed to have released now though.
In the datasheet at page 10-14. PM me an email if you are interested in the datasheet for the 9LPRS477C (9LPRS477CKL used on the GBT board, 9LPRS477BKL on M3A and Sapphire, I expect it's very similar to the C version but without a gpu frequency).
Coming up
You used an phenom while you dumped i2c-0 under ubuntu? I wonder why you do not get interfaces at 0x4c and 0x47.
Yep. Probably not because my BIOS doesn't use SVID interface but the DFI/Sapphire does.
At 0x4c seems to be the svi interface. It's dumps change if i change the cpu vid or the nb vid in the bios. So with an simple module it's possible to monitor the cpu and nb voltage via that interface on the sapphire board. Gotta figure out the encoding but the dump even changes with 0.00625V step increases in the bios. This increments can not be covered by the VID's encoding the CPU uses, those only allow 0.0125V increments.
But the VIDs are different to voltages - are you saying SVID can allow finer voltage control?

If so, then yup that's true.