Quote Originally Posted by KTE View Post
Nice. Why is that showing maximum PLL oc at 280MHz?
Still figuring out how the ref HT is generated out of all those settings. The board is not limited to 280MHz.
Quote Originally Posted by KTE View Post
Where's the register encodings mentioned? I've not come across them yet, would be cool. Thanks.
In the datasheet at page 10-14. PM me an email if you are interested in the datasheet for the 9LPRS477C (9LPRS477CKL used on the GBT board, 9LPRS477BKL on M3A and Sapphire, I expect it's very similar to the C version but without a gpu frequency).

You used an phenom while you dumped i2c-0 under ubuntu? I wonder why you do not get interfaces at 0x4c and 0x47. At 0x4c seems to be the svi interface. It's dumps change if i change the cpu vid or the nb vid in the bios. So with an simple module it's possible to monitor the cpu and nb voltage via that interface on the sapphire board. Gotta figure out the encoding but the dump even changes with 0.00625V step increases in the bios. This increments can not be covered by the VID's encoding the CPU uses, those only allow 0.0125V increments.