ABit AX78 Overclocking/Stability

[KTE]

No, not stable
3000/3000/2700/2800 1.344v ID failed just after 2 hours
3000/2900/2700/2800 passed stock volts though.

I think I've reached a limit whereafter voltage won't make a difference. I only want to add upto 1.45v real max, no more but I don't think I can get more out of core1/2/3. Core0 may do 3.1G, I know it'll bench/load test it but it may not be idle stable after 1-2 hours.

Hmm 2.10.1 is an old version. SB700 support was added at 2.10.3 and the latests is 3.0.1. Starting with 2.10.4 there is also a module for your sensor chip available (w83627ehf).
You need SB700 support in i2c-piix4 to dump the i2c/smbus devices.

Ah ok, thanks. The version I downloaded said it was the latest but the version number was exactly what I posted. Nevermind

Thanks, I got my hands on the spec of the clock chip they used on the M3A and the Sapphire board, the GBT uses an very similar chip. I also have the specs of the clock chip used on the M2A-VM. So i'll try to write a small kernel module to read out ref HT and pci express clocks. It might be extended to change those frequencies in the future. Depends on how much time it will take.

Great. Is there a pin on the I/O chip of those chips reading the HT Ref?
I also have the GBT 780G again BTW.

Say core0 need 1.3V to be stable at 3GHz but it is not stable at say 1.45V.
Core2 is stable up to 2.7GHz with 1.3V and is also stable at 3GHz with 1.45V.
In this situation with 1.45V applied it might be core0 causing the freeze.
It's a vague theory and i don't like those.

Agreed, it could be. That's a good point, I'll have to think that over - how to eliminate. Maybe testing by disabling one core at a time would be ok?

I'm not sure but, if you disable a core in Windows but reboot setting say 3000 across all cores in BIOS -- does the 4th core get set to 3000 aswell or do they keep it at stock on boot?

I got into Ubuntu, ran it and got all I/O details fine. Was posting them to you but the system froze (3000/3000/3000/3000 1.355v). So have to go back into now and will post.

[justapost]

Great. Is there a pin on the I/O chip of those chips reading the HT Ref?
I also have the GBT 780G again BTW.

Currently I play with the clockchip of the 690G.

http://www.idt.com/products/getDoc.cfm?docID=18459722
The specs say "An SMbus interface allows full control of the device"

This is a dump of the smbus registers "i2cdump 0 0x64 s"

   0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 07 ff f0 ff 00 00 62 01 14 e0 e0 54 7d f8 17 de    ?.?...b????T}???
10: 76 f8 17 04                                        v???

The specs say what those mean. Gotta figure out how to read those registers from within a kernel module. That module will provide devices in /proc or /dev whom can be used to read(write) the values.
I'm still very busy at work till june. Have two weeks holiday then and will work on that module then. Meanwhile i'll do some theory (reading other sensor chip module code and stuff at smbus.org).

Agreed, it could be. That's a good point, I'll have to think that over - how to eliminate. Maybe testing by disabling one core at a time would be ok?

I'm not sure but, if you disable a core in Windows but reboot setting say 3000 across all cores in BIOS -- does the 4th core get set to 3000 aswell or do they keep it at stock on boot?

I guess windows does not use the downcore method for unused codes so it will run at 3GHz but do nothing (beside freezing maybe).
On the M3A I disabled cores 3 and 4 via bios and had no freezing issues at 3GHz so I assume disabling via bios is save.
A good test case should be:
1. Disable all cores beside core0 and find the higest voltage and frequency the core can handle. Use the higest voltage as the top limit in 2.
2. Add cores1-3 individual and find the highest voltage and frequency for that core.
3. Use the minimum of the max voltages of all four cores and find the max frequency for each core at this voltage.
4. Enjoy your overclocked system

I got into Ubuntu, ran it and got all I/O details fine. Was posting them to you but the system froze (3000/3000/3000/3000 1.355v). So have to go back into now and will post.

I hope it was due to your multis this time.

[Rammsteiner]

But why are you guys reading/disabling/modifying all those bus things? Are you like fixing the SB600 or something as it should have been.

Also KTE, the results you're getting now, did you get any of these results on any of your other boards like MSI, GB or what else you have? Because it's a little unclear atm for me as you post in all the threads for specific boards telling you get x results and I dont understand anymore if that's only with the Abit or if you got it on other boards as well.

My 4th core (in AOD Core 3) was able to run 5 minutes 2.9Ghz stock Volts. But But AOD is too buggy for me to actually continue testing. If you put all the core multi's at once system might freeze and for some reason some values give me 'Machine Check Exception' BSOD. Well, Im done with it.

Either enable Crossifre on 780a boards, which wont happen most likely, or get SB750 FAST.

[justapost]

But why are you guys reading/disabling/modifying all those bus things? Are you like fixing the SB600 or something as it should have been.

First i want to track down what killed my chip. Second with a module for the clock generator it would be possible to change the ref HT in realtime.
Third, it's a nice playground to get familar with i2c/smbus and i really love getting this lowlevel access to all those chips.

My 4th core (in AOD Core 3) was able to run 5 minutes 2.9Ghz stock Volts. But But AOD is too buggy for me to actually continue testing. If you put all the core multi's at once system might freeze and for some reason some values give me 'Machine Check Exception' BSOD. Well, Im done with it.

Either enable Crossifre on 780a boards, which wont happen most likely, or get SB750 FAST.

You can use sam2008's tool or crystalcpu and modify the multis for each core in the p-state-0 register 0xC0010064.
I wrote in the Official DFI thread at page #24 how you can do that. I'll post a short howto in the Unified thread now.

[Rammsteiner]

Awesome, thx a lot.

Hopefully it will give better results. I think VID options in AOD were bugged too. CPU-Z read 1.232Vcore while AOD set 1.3V as set in BIOS. But without opening AOD CPU-Z read 1.29V which it always did.

Really considering another brand motherboard though when SB750 is out. The noises coming from this board and other issues make me concerned that it might at some point put its finger up in my face and kill everything.

[KTE]

Currently I play with the clockchip of the 690G.

http://www.idt.com/products/getDoc.cfm?docID=18459722
The specs say "An SMbus interface allows full control of the device"

Nice. Why is that showing maximum PLL oc at 280MHz?

This is a dump of the smbus registers "i2cdump 0 0x64 s"

   0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 07 ff f0 ff 00 00 62 01 14 e0 e0 54 7d f8 17 de    ?.?...b????T}???
10: 76 f8 17 04                                        v???

The specs say what those mean. Gotta figure out how to read those registers from within a kernel module. That module will provide devices in /proc or /dev whom can be used to read(write) the values.
I'm still very busy at work till june. Have two weeks holiday then and will work on that module then. Meanwhile i'll do some theory (reading other sensor chip module code and stuff at smbus.org).

Where's the register encodings mentioned? I've not come across them yet, would be cool. Thanks.

I guess windows does not use the downcore method for unused codes so it will run at 3GHz but do nothing (beside freezing maybe).
On the M3A I disabled cores 3 and 4 via bios and had no freezing issues at 3GHz so I assume disabling via bios is save.
A good test case should be:
1. Disable all cores beside core0 and find the higest voltage and frequency the core can handle. Use the higest voltage as the top limit in 2.
2. Add cores1-3 individual and find the highest voltage and frequency for that core.
3. Use the minimum of the max voltages of all four cores and find the max frequency for each core at this voltage.
4. Enjoy your overclocked system

Yeah I'm going to test something similar.

I hope it was due to your multis this time.

Yeah, speed was unstable

Also KTE, the results you're getting now, did you get any of these results on any of your other boards like MSI, GB or what else you have? Because it's a little unclear atm for me as you post in all the threads for specific boards telling you get x results and I dont understand anymore if that's only with the Abit or if you got it on other boards as well

MSI and Abit, nothing else yet. Haven't had GBT DQ6/DS5 for a long time now, but do have GBT 740G and 780G boards.
Borrowing spare MSI from work friend, mines dead.

[justapost]

Nice. Why is that showing maximum PLL oc at 280MHz?

Still figuring out how the ref HT is generated out of all those settings. The board is not limited to 280MHz.

Where's the register encodings mentioned? I've not come across them yet, would be cool. Thanks.

In the datasheet at page 10-14. PM me an email if you are interested in the datasheet for the 9LPRS477C (9LPRS477CKL used on the GBT board, 9LPRS477BKL on M3A and Sapphire, I expect it's very similar to the C version but without a gpu frequency).

You used an phenom while you dumped i2c-0 under ubuntu? I wonder why you do not get interfaces at 0x4c and 0x47. At 0x4c seems to be the svi interface. It's dumps change if i change the cpu vid or the nb vid in the bios. So with an simple module it's possible to monitor the cpu and nb voltage via that interface on the sapphire board. Gotta figure out the encoding but the dump even changes with 0.00625V step increases in the bios. This increments can not be covered by the VID's encoding the CPU uses, those only allow 0.0125V increments.

[KTE]

Still figuring out how the ref HT is generated out of all those settings. The board is not limited to 280MHz.

According to that data, only HT to 280MHz is defined for the SB600 PLLs with X2s. They don't have data for K10 in there, the new docs are supposed to have released now though.

In the datasheet at page 10-14. PM me an email if you are interested in the datasheet for the 9LPRS477C (9LPRS477CKL used on the GBT board, 9LPRS477BKL on M3A and Sapphire, I expect it's very similar to the C version but without a gpu frequency).

Coming up

You used an phenom while you dumped i2c-0 under ubuntu? I wonder why you do not get interfaces at 0x4c and 0x47.

Yep. Probably not because my BIOS doesn't use SVID interface but the DFI/Sapphire does.

At 0x4c seems to be the svi interface. It's dumps change if i change the cpu vid or the nb vid in the bios. So with an simple module it's possible to monitor the cpu and nb voltage via that interface on the sapphire board. Gotta figure out the encoding but the dump even changes with 0.00625V step increases in the bios. This increments can not be covered by the VID's encoding the CPU uses, those only allow 0.0125V increments.

But the VIDs are different to voltages - are you saying SVID can allow finer voltage control?

If so, then yup that's true.

[justapost]

According to that data, only HT to 280MHz is defined for the SB600 PLLs with X2s. They don't have data for K10 in there, the new docs are supposed to have released now though.

Hmm but i ran an X23800 at 3GHz on this mobo. That is only possible with an 300MHz ref HT. I think bytes 11 and 12 play the main role for the ref HT.

Yep. Probably not because my BIOS doesn't use SVID interface but the DFI/Sapphire does.
But the VIDs are different to voltages - are you saying SVID can allow finer voltage control?
If so, then yup that's true.

There is a PCI register showing whether this SVI SMbus interface exists or not. If Bit 3 is set on your system the interface is unused.
It turned out i was wrong with the chip at 0x4c. This is the thermal interface. Four bytes change their values enormous if I build the kernel and sligthly when in idle.