Intel Details Nehalem uArch Improvements - 256KB L2, 8MB L3 Confirmed

[JumpingJack]

I wouldn't say that, amd can't get their imc to clock well, but look at ibm's power6 monster, that is manufactured on a 65nm soi process with an imc and yet scales to 4.5ghz+ on air supposedly (though I haven't heard anything on the temps). As for hyperthreading, that failed previously because of the poor netburst design, the concept of it is quite good. Once multithreaded software appears more, you'll see the benefits, not to mention the much shorter pipeline to transfer data will help out with the hyperthreading usefullness

IBM also leaks like a sieve .. achieving 4.5 GHz on thier 65 nm process was manipulated through both architecture and process conditions to produce high clocks. This is because IBM moved away from an OoO engine to more in order, and simplied the engine to minimize the deepest FO4 delay.

http://www.research.ibm.com/journal/rd51-6.html (everything you want to know)

The most important article is this one:
http://www.research.ibm.com/journal/rd/516/curran.pdf

Various frequency/cycle-time targets were evaluated
during an exploratory phase. A cycle time corresponding
to 13-FO41 inverter delays was selected based on the
fastest known techniques to achieve back-to-back
execution of 64-byte dependent, fixed-point instructions.

IBM restricted themselves to a cycle time of only 13 FO4 delays for the fixed point latency, this is pretty short all things considered... but also means your circuits must be very very simply (transistor lean). Table 1 shows the FO4 delay reduction from power 5 to power 6, for both simple fixed point and fused multiply and add. IBM went in with the preconception of achieving high clockspeeds, and achieved it through this and process:

The POWER6 processor chip is fabricated using the IBM
high-performance 65-nm partially depleted SOI process
with 40-nm gate length n-FETs, 35-nm gate length
p-FETs, and 1.05-nm gate oxides

This gate thickness is about 0.15-0.2 nm thinner than either AMD or Intel at 65 nm (their reported thicknesses were 1.3 nm and 1.25 nm respectively as I recall). Translation, IBM's power 6 is a power sucker.

http://www.research.ibm.com/journal/rd/516/berridge.pdf

Figure 12 shows their leakage curve, following an exponential you would expect for tunneling current in such a thin gate. At nominal operating conditions for a 4.5 GHz processor which is about 8.5 ps, their leakage just through the gate is about 80 Watts.

This is doable for the market that Power6 is designed for, which are high class enterprise systems where cooling solutions can be specifically designed and, if throughput is high enough, the higher power can be justified.

IBM's design and the process tweaks they made to get there is a very special application, and is completely in appropriate for the markets AMD or Intel service... extrapolating or implying that AMD could do a 4.5 GHz because IBM can do 4.5 GHz is simply incorrect, and anyone counting on that should not hold their breath... it just ain't gonna happen.

Jack