Intel Details Nehalem uArch Improvements - 256KB L2, 8MB L3 Confirmed

[Carfax]

256 bit computing is coming!

[onewingedangel]

I just hope all this doesnt mean the return of the cold bug.
integrated memory controllers tend to have cold bugs.

in a few weeks with the A64, I bought 13 of them to find one, that didnt have a cold bug.
I sure as hell couldnt afford to do that with a Intel chip.

The problem with this assertion though is that we haven't seen a mainstream IMC equiped chip that doesn't use SOI, so whether its the SOI or IMC at fault is questionable.

[Movieman]

Wow! Wonder who's going to be the first at Xs to get one of these!

[RPGWiZaRD]

I'm interesthing how Intel going IMC affects overclocking, still I think these are going to be such awesome chips even if overclockability goes down from C2D a bit it won't matter.

[[XC] gomeler]

The problem with this assertion though is that we haven't seen a mainstream IMC equiped chip that doesn't use SOI, so whether its the SOI or IMC at fault is questionable.

We have seen northbridges built on bulk and they also cold-bug, not as badly as AMD chips though. I'd be fine with a cold-bug around -90C or so, prime 2-stage cascade range

[K404]

if anything they'de go UP.

Core CPU
64k fast cache
6mb medium cash


nehalem
64k fast cache
2mb somewhat fast cache speed cache
8mb medium cache

For nehalem- where are you getting the 2MB somewhat fast cache from?

Im not great at microprocessor definitions, but using Phenom as a comparison, benching doesnt seem to get a boost from the L3 cache. Phenom essentially acts just like a 512MB cache/core AM2 for single-thread apps.

Im well aware that the cache design is different, but IF the L3 isnt used to keep data close to the CPU for benching, wont performance take a massive hit from only having 256KB for each core, compared to 6MB that we have now?

(this is only for single thread discussion, which is still fundamental to computer operations. Before anyone says multi-thread is the future. it WILL be, but isnt yet, not properly)

[Blauhung]

I still get wood over the idea of 6GB unbuffered 6 channel DDR3 directly feeding 16 threads of DC'ing goodness.

Do Want!

Oh and they look really pretty on a wafer, I was just admiring some Nehalem and Dunnington today.

[Kunaak]

The problem with this assertion though is that we haven't seen a mainstream IMC equiped chip that doesn't use SOI, so whether its the SOI or IMC at fault is questionable.

yes, thats true.
however, I do remember the instant death from high vdimm on the IMC first gen CPU's.
remember that clearly, since I killed 4 before anyone figured out what was killing the CPU's.
and that was at low voltages at the time, like 2.8 volts. (which sounds so weird now talking about DDR3 and such)

the IMC definatly has me holding back to see what happens.

[K404]

yes, thats true.
however, I do remember the instant death from high vdimm on the IMC first gen CPU's.
remember that clearly, since I killed 4 before anyone figured out what was killing the CPU's.
and that was at low voltages at the time, like 2.8 volts. (which sounds so weird now talking about DDR3 and such)

the IMC definatly has me holding back to see what happens.

hasnt that also happened in a few cases for phenom as well?

[Face]

Some info on Larabee as well:

Of course, what many were really waiting for Gelsinger to discuss during the pre-briefing was Larrabee, and Intel saved the best for last there. Larrabee, Gelsinger says, will combine a large array of Intel Architecture (i.e. x86) cores with a brand-new cache architecture, a new vector instruction set (Intel wouldn't comment on Larrabee's relationship with AVX), and a new vector processing unit. Gelsinger specified that Larrabee's programmable architecture will allow it to accelerate anything from high-definition video and audio processing to physics, artificial intelligence, and global illumination.

Not only that, but Gelsinger also confirmed Larrabee will be compatible with DirectX and OpenGL application programming interfaces. In other words, while Intel will be pushing for different rendering paradigms like ray tracing, the company won't have to wait on developers to make its silicon useful to gamers—Larrabee should be able to run existing games.

Intel plans to show its first demos of Larrabee in action later this year, with a product launch to follow in either 2009 or 2010. So far, Intel says response to Larrabee from independent software vendors has been "tremendous."

Larrabee will thrust Intel into the discrete graphics market in a very large way. Not only does Intel plan to compete directly with NVIDIA and AMD/ATI in terms of straight graphics processing, it also plans to deliver physics processing on a discrete Larrabee solution. Smith hinted at physics processing as being one of the key strengths of Larrabee's design.

When asked about Intel's expected position in the market against NVIDIA and AMD/ATI, Smith said that "[Intel] will do well."

http://techreport.com/discussions.x/14361

http://www.news.com/8301-13579_3-989...g=2547-1_3-0-5

http://www.tomshardware.com/2008/03/...md-ati_nvidia/

[safan80]

I just hope all this doesnt mean the return of the cold bug.
integrated memory controllers tend to have cold bugs.

Also chances are it won't OC too well to begin with either.

[BullGod]

Intel Corporation's Multicore Architecture Briefing



TukwilA

The new superchip from Intel.

[XS Janus]

BullDog I need a new Monitor for THAT picture!
Thanks.

But Tukwilla is not Nehalem.

OT: This will trickle slowly to regular desktop machines IMO.
But never mind. Imagine how FAST web surfing will be with a couple of these babies!

[Helmore]

Does anyone have any idea on what the transistor count is on Larrabee? I'd like to know just to compare to current and future GPUs even though it's pretty meaningless from a performance standpoint.

[STaRGaZeR]

ever heard about a thumbnail?

[vmsein]

I just sure hope that the market doesn't continue to move in the "everybody has their own proprietary platform and we can't interchange components" direction started by nvidia and their SLi tech. Please, no more restrictions on which components an enthusiast chooses to use on their platform of choice. Here's hoping that if Larabee turns out to be a competitive product, we can use it where we choose to use it. Although it would appear that a system running Nehalem will be a great place to start!

[Movieman]

I still get wood over the idea of 6GB unbuffered 6 channel DDR3 directly feeding 16 threads of DC'ing goodness.

Do Want!

Oh and they look really pretty on a wafer, I was just admiring some Nehalem and Dunnington today.

You,You tease you!
What I want a little clarification on is does this use regular DDR3 or??????

[Nedjo]

You,You tease you!
What I want a little clarification on is does this use regular DDR3 or??????

Well it says RDDR3, and U DDR3 (registered and unbuffered)

[Movieman]

Well it says RDDR3, and U DDR3 (registered and unbuffered)

Thank you, I read that and went right over it..
Muchas gracias!

[Nedjo]

so this is the finall adios to FBDIMM?

[Metroid]

HyperThreading technology is back now called Simultaneous Multi-Threading (SMT).

Tock: New architecture 65nm Core 2 Duo
Tick: Shrink of previous microarchitecture 45nm Penryn 2007

Tock: New architecture 45nm Nehalem
Tick: Shrink of previous microarchitecture 32nm Westmere 2009

Tock: New architecture 32nm Gesher

It is time to save some money.

Metroid.

[zanzabar]

shouldent all of this lead to lower clocks and since we have 4ghz quads now how much improvement will we see with a possible 2ghz quad with this stuff, and Hypoer threading dosnt work historically so dont expect it to help and it wont oc well if history proves the imc right


and dont forget that lga775 still has the hex core coming this summer and it should still oc well

[Blauhung]

so this is the finall adios to FBDIMM?

forr DP stuff yes. MP stuff on the other hand, kinda. I don't know the details, but there's something in the works.

But Movieman, I believe since the memory controler on Nehalem is designed with both desktop and DP workstation in mind, both platforms have the option to use either ECC registered or non-ECC DDR3. Hence the wood, 6 channels of enthusiast grade high binned DDR3.

[hollo]

and dont forget that lga775 still has the hex core coming this summer and it should still oc well

for lga775?

[AliG]

I wouldn't say that, amd can't get their imc to clock well, but look at ibm's power6 monster, that is manufactured on a 65nm soi process with an imc and yet scales to 4.5ghz+ on air supposedly (though I haven't heard anything on the temps). As for hyperthreading, that failed previously because of the poor netburst design, the concept of it is quite good. Once multithreaded software appears more, you'll see the benefits, not to mention the much shorter pipeline to transfer data will help out with the hyperthreading usefullness