Intel Details Nehalem uArch Improvements - 256KB L2, 8MB L3 Confirmed

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Nehalem actually steps one notch beyond the "native" quad-core design of K10, integrating the cache hierarchy more closely together, by making the L3 cache inclusive with the L2 arrays, thus allowing for shorter data-coherent update between the threads, just by picking an L3 cache line.
Of course, this comes at the cost of totally available L3 size, as follows: 8 - (4*256K) = 7MB. That's the reason for the rather shy L2 per core, not because of the pure low latency design intentions.

No, total of 8MB cache is available.

Read it again: inclusive relationship with the L2 arrays!