Quote Originally Posted by Cronos View Post
This errata has two implications.

First, the probability of error showing itself is considerably higher on low-end boards than on high-end ones.

And second, even on high-end board we can expect reduced FSB oc potential
from all C0 stepping Yorkfields, which in fact is supported so far by experimental data.

The possible good news for all those who are waiting for more affordable Q9450/9550, is that we can expect C1 stepping to be better FSB clocker. But this is only speculation for now, only the practice will tell.

Higher FSB is especially important for those who want to fully realize all DDR3 potential, as having fast DDR3 with slow FSB is totally pointless.
Couple of questions:
I still dont get what the error is. Is it the fact that it wont have a high FSB potential because of the FSB voltage problem?
What are these errors and would you know if you got one as in your Computer keeps rebooting or BSODs etc. ?

Secondly I dont see anywhere stating that it only has to deal with 4 Layer PCB's. Sorry to ask these questions but I think I am in the clear. Im only using DDR2 which a higher fsb would always be nice but im sticking with my 400 FSB. Which i dont consider to be very high as ive been using this setting for the last year and a half on my MB's.

Secondly If someone could show where it states it only affects 4 Layer pcbs that would be great, As that would rule me out pretty much ( as stated above dont care too much about achieving higher than a 400 fsb) as I have a 780i and seeing as the 680i was a 6 layer PCB i can only assume that the 780i is also LOL.

Funny thing is this errata has been out since dec 20th. but its the first im seeing of this- and it states many places that its only in experimental situations theyve seen this- Im assuming if my Chip was having issues i wouldnt be able to have it Prime95 stable for 8 hrs on both blend and Small FFT (Which is what i use to "test" for stability and have passed) ..

Thanks for any help in advance!