All C0 Yorkfields have potential instability problem, confirmed by Intel

[Cronos]

This errata has two implications.

First, the probability of error showing itself is considerably higher on low-end boards than on high-end ones.

And second, even on high-end board we can expect reduced FSB oc potential
from all C0 stepping Yorkfields, which in fact is supported so far by experimental data.

The possible good news for all those who are waiting for more affordable Q9450/9550, is that we can expect C1 stepping to be better FSB clocker. But this is only speculation for now, only the practice will tell.

Higher FSB is especially important for those who want to fully realize all DDR3 potential, as having fast DDR3 with slow FSB is totally pointless.