PLL voltage is referred to VCCPLL or PLL VCC with nominal value 1.50v+/-5%, and it is input voltage applied to CPU across pin 23 (as intel datasheets stated for Conroe). VCCPLL provides isolated power for internal processor FSB PLLs.
A phase-lock, or phase-locked, loop (PLL) is an electronic control system that generates a signal that is locked to the phase of an input or "reference" signal.
This means internal processor FSB PLLs are circuit responsibles to lock the phase of external FSB (the FSB of the external bus between northbridge and cpu) with internal processor bus.
In very simple words these circuits are responsible to sincronyze the external FSB with internal processor bus where flow all signals outuput from FSB to internal processor bus (command and data) and viceversa.
Now some processors have better internal FSB PLLs than another one, and this mean that that first rpocessor has higher FSB wall. If you want to help to raise CPU FSB wall you have to raise pll voltage because in this way internal processor FSB PLLs become more stable.
I hope my explanation was clear about very diffucult argument with my little english.

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