With the exception of the memory voltage the others are most likely higher then they need to be. I just punched all those settings in knowing they would have no influence on how the memory clocked. The required NB voltage is going to be more the result of the FSB speed rather then memory speed.

Code:
CPU Feature Page
Thermal Management Control................Disabled
PPM (EIST) Mode...........................Disabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Disabled
Execute Disable Bit.......................Enabled
Virtualization Technology.................Disabled
Core Multi-Processing.....................Enabled

Main BIOS Page
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Enabled
O. C. Fail Retry Counter..................0
CLOCK VC0 Divider.........................Auto
CPU Clock Ratio...........................8x
CPU Clock.................................465 MHz
Boot Up Clock.............................Auto
DRAM Speed................................333/800
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

Voltage Setting Page 
CPU VID Control...........................1.50000V
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.10V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.655V
CPU VTT Voltage...........................1.393V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
GTL REF Voltage Control...................Disabled
CPU GTL1/3 REF Volt.......................N/A
CPU GTL 0/2 REF Volt......................N/A
North Bridge GTL REF Volt ................N/A

DRAM Timing Page
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................3
Precharge Delay (tRAS)....................15
All Precharge to Act......................4
REF to ACT Delay (tRFC)...................48
Performance Level.........................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................2
Write to PRE Delay (tWR)..................13
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............4
Ranks Read to Read (tRDRD)................5
Ranks Write to Read (tWRRD)...............4
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................4

Read Delay Phase Adjust Page
Channel 1 Phase 0 Pull-In.................Enabled
Channel 1 Phase 1 Pull-In.................Enabled
Channel 1 Phase 2 Pull-In.................Enabled
Channel 1 Phase 3 Pull-In.................Enabled
Channel 1 Phase 4 Pull-In.................Enabled

Channel 2 Phase 0 Pull-In.................Enabled
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Enabled
Channel 2 Phase 3 Pull-In.................Enabled
Channel 2 Phase 4 Pull-In.................Enabled

Clock Setting Fine Delay Page
Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 133ps
DIMM 2 Clock fine delay...................Current 512pd
DIMM 1 Control fine delay.................Current 578ps
DIMM 2 Control fine delay.................Current 345ps
Ch 1 Command fine delay...................Current 845ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 133
DIMM 4 Clock fine delay...................Current 445
DIMM 3 Control fine delay.................Current 423
DIMM 4 Control fine delay.................Current 412
Ch 2 Command fine delay...................Current 845

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto