Quote Originally Posted by justapost View Post
The first (worst case) value is calculated. But after Dram training it get's optimized by a training method similar to memtest.
The value diminishes as long as the patterns are read correct.
This training leads to different results (+-1ns) after each boot. The value also is smaller if i apply more volts to the ram.
That's why i mentioned it in the first place.
I wonder what other (L3 related) latencies are configured in a similar way.
Test with DQS Drive Strength enabled settings, it helps in the same way here.

How do you calculate this?
By using the common formula which cooling product makers use to calculate chip power dissipation and cooling ratings. Same with whats used to build phase change units and so on although most common people don't know of it. Take my example.

Phenom 9500 95W TDP chip has 18.9A per core @ 1.232V = 93W

Using 95W as reference stock chip power, say I oc'd to 2.5GHz at 1.4V:

95 x (2500/2200) x (1.4²/1.232&#178

139.4W power

Code:
Pn = Pt x (vn/vt) x (Un²/Ut²)
TDP - thermal design point (Pt = Power [W])
Default Voltage (Ut = Voltage [V])
Default Frequency (νt = Frequency [MHz])
Overclocked Voltage (Un = [V])
Overclocked Frequency (vn = [V])
Another question: What is the max ref HT you can boot with with an 9xnb multi?
212MHz

I'll test more later with a better BIOS (flashing back to older ones without errata patch).