Quote Originally Posted by KTE View Post
Yeah, it calculates a total aggregate based on latencies and NB clocks so indeed it would definitely make a large difference to the DCT performance. I've tried 40ns vs 50ns at 1066 5-5-5-15 2T, good gains.
The first (worst case) value is calculated. But after Dram training it get's optimized by a training method similar to memtest.
The value diminishes as long as the patterns are read correct.
This training leads to different results (+-1ns) after each boot. The value also is smaller if i apply more volts to the ram.
That's why i mentioned it in the first place.
I wonder what other (L3 related) latencies are configured in a similar way.

Quote Originally Posted by KTE View Post
As for NB DID, my BIOS gives the following options:
Bits - Divisor
000b Divide-by 1
001b Divide-by 2
010b Divide-by 4
011b Divide-by 8
100b Divide-by 16
Well choosen labels.

Quote Originally Posted by KTE View Post
That means there's a bad current leakage problem at ~1.4V.

For a 2.2GHz 1.23V 95W TDP chip, the power needed to be dissipated at 2.7GHz 1.44V is 160W providing core current supply is kept constant. So no wonder you need liquid.
How do you calculate this?

Another question: What is the max ref HT you can boot with with an 9xnb multi?