Official DFI LanParty UT X38-T2R(and LT) Discussion/Review/Overclock/Guide Thread

[eva2000]

Thanks will try that.. in meantime

2x1GB Crucial Ballistix PC2-8500 Tracer @675Mhz 5-5-5-9 at 2.55v

Swapped the dimm slots for this pair of Crucial Ballistix PC2-8500 Tracers from dimm slot 2+4 (yellow slots) to 1+3 (green slots) and seems can overclock a bit better. I can now hit 675Mhz 5-5-5-9 at 2.55v - highest ever CAS5 memory clock for this pair of Crucial Ballistix PC2-8500 Tracers at Super Pi 32M passable speeds!

Still 32M time seems around 4-10 seconds slower at 3600Mhz mark than 965P/P35 chipset. I guess the loosened internal latencies on X38 allow memory to clock higher but at a cost of clock for clock performance ? Still I am looking forward to 3dmark benchmarks with X38 x16+x16 PCI-E slots



Click image for larger version below

Super Pi 1M



Super Pi 32M





DFI LP LT X38-T2R Bios Settings

PC Health Status
Adjust CPU Temp: +7C

CPU Feature
- Thermal Management Control: Disabled
- PPM(EIST) Mode: Disabled
- Limit CPUID MaxVal: Disabled
- CIE Function: Disabled
- Execute Disable Bit: Disabled
- Virtualization Technology: Disabled
- Core Multi-Processing: Enabled

Exist Setup Shutdown: Mode 2
Shutdown after AC Loss: Disabled
CLOCK VC0 divider: AUTO
CPU Clock Ratio Unlock: Enabled
CPU Clock Ratio: 8x
- Target CPU Clock: 3601
CPU Clock: 450
Boot Up Clock: AUTO
DRAM Speed: 266/800
- Target DRAM Speed: 1353
PCIE Clock: 100mhz
PCIE Slot Config: 1X 1X

CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
SATA Spread Spectrum: Disabled

Voltage Settings
CPU VID Control: 1.2875
CPU VID Special Add: AUTO
DRAM Voltage Control: 2.55
SB Core/CPU PLL Voltage: 1.51
NB Core Voltage: 1.643
CPU VTT Voltage: 1.393
Vcore Droop Control: Enabled
Clockgen Voltage Control: 3.45v
GTL+ Buffers Strength: Strong
Host Slew Rate: Weak
GTL REF Voltage Control: Disable
x CPU GTL1/3 REF Volt: 110
x CPU GTL 0/2 REF Volt: 110
x North Bridge GTL REF Volt: 110

DRAM Timing
- Enhance Data transmitting: FAST
- Enhance Addressing: FAST
- T2 Dispatch: Enabled

Clock Setting Fine Delay
Ch1 Clock Crossing Setting: More Aggressive
- DIMM 1 Clock fine delay: 6
- DIMM 2 Clock fine delay: 7
- Ch 1 Command fine delay: 11
- Ch 1 Control fine delay: 8


Ch2 Clock Crossing Setting: More Aggressive
- DIMM 3 Clock fine delay: 6
- DIMM 4 Clock fine delay: 7
- Ch 2 Command fine delay: 11
- Ch 2 Control fine delay: 6

Ch1Ch2 CommonClock Setting: More Aggressive

Ch1 RDCAS GNT-Chip Delay: Auto
Ch1 WRCAS GNT-Chip Delay: Auto
Ch1 Command to CS Delay: Auto

Ch2 RDCAS GNT-Chip Delay: Auto
Ch2 WRCAS GNT-Chip Delay: Auto
Ch2 Command to CS Delay: Auto (where cpuz sees 1T or 2T SETTING)

CAS Latency Time (tCL): 4
RAS# to CAS# Delay (tRCD): 4
RAS# Precharge (tRP): 4
Precharge Delay (tRAS): 5
All Precharge to Act: 4
REF to ACT Delay (tRFC): 30
Performance LVL (Read Delay) (tRD): 5

Read delay phase adjust: Enter

Ch1 Read delay phase (4~0)
- Channel 1 Phase 0 Pull-In: Auto
- Channel 1 Phase 1 Pull-In: Auto
- Channel 1 Phase 2 Pull-In: Auto
- Channel 1 Phase 3 Pull-In: Auto
- Channel 1 Phase 4 Pull-In: Auto

Ch2 Read delay phase (4~0)
- Channel 2 Phase 0 Pull-In: Auto
- Channel 2 Phase 1 Pull-In: Auto
- Channel 2 Phase 2 Pull-In: Auto
- Channel 2 Phase 3 Pull-In: Auto
- Channel 2 Phase 4 Pull-In: Auto

MCH ODT Latency: AUTO
Write to PRE Delay (tWR): 14
Rank Write to Read (tWTR): 11
ACT to ACT Delay (tRRD): 3
Read to Write Delay (tRDWR): 8
Ranks Write to Write (tWRWR): 4
Ranks Read to Read (tRDRD): 5
Ranks Write to Read (tWRRD): 4
Read CAS# Precharge (tRTP): 3
ALL PRE to Refresh: 4

Managed to shave 4 seconds off 32M time and drop memory latency a tad