High memory voltage on Phenom...

[Lightman]

I would not run it at 2.4 V given the information kindly passed in this thread by various users.

If you leave it in auto, the memory will default to the JEDEC standard voltage and speeds that will operate at that voltage -- if you want the faster capability, then a) you need to manually set it, or b) if you have an nVidia chipset and the memory is SLI capable, then let the nVidia BIOS SLI option set it for you.

Hi JumpingJack

Not only nVidia chipsets can do that. Our AMD Chipsets also can set EPP profile from extra SPD records That's why my memory at default is trying to run DDR 1066 5-5-5 @2.212V Of course Gigabyte was kindly enough to put an option to disable EPP profiles and/or voltages in BIOS .

[justapost]

AMD will know if you ran it out of spec I suspect ... they will decline the RMA most likely.

Do you know the spec's for ram voltages on K10? I can not find that info on the amd website.
EDIT: #72
Anyway i would not try to get a b3 this way. If we ever need a quadcore workstation at work I can but my well tested one in that machine and the new one will end up in my machine for further testing.

[nemrod]

Can someone who believes in this try to explain it with some technically sound knowledge? It makes little sense to me, if I look to the physics involved unless we're missing something crucial, in which case I want to know what it is.

I believe this is related to CMOS latch-up. Then I think that the circuit design to protect from latch-up increase the input capacitance (and then reduce frequency response). I think phenom work well with low voltage memory because they have reduce protection and then associate parasitics. The drawback is you have to respect absolute maximum ratings.

[KTE]

I believe this is related to CMOS latch-up. Then I think that the circuit design to protect from latch-up increase the input capacitance (and then reduce frequency response). I think phenom work well with low voltage memory because they have reduce protection and then associate parasitics. The drawback is you have to respect absolute maximum ratings.

That's a thoughful suggestion but I believe latchups are a very basic design problem which are dealt with long ago in CMOS design as there are many ways around it which have been implemented since very long now such as reducing Q1 gain and it would really be poor engineering to forego this. A latchup can occur in any system with just radiation, ESD, power spikes or high transient currents since it mainly occurs where high voltage transients exists and wherever you have large currents present rather than this scenario with low voltages and currents. When you have this defect it will destroy the components involved so you also have to cut down the current to the circuit by a very critical amount rather than the voltage. 1.8V-2.2V vs 2.2-2.4V doesn't seem like the amounts applicable to bypass this phenomenan since this seems to occur only when affecting the IMC voltage by increasing it. Don't you think?

[nemrod]

I don't know exactly how it's design for a cpu, and I 'm not enough aware of cmos device. I've seen different way to reduce latch-up with circuits solutions and/or technological solutions. But I only know I've seen this kind of problem with a cmos amplifier:
http://focus.ti.com/lit/ds/symlink/tlc2652a.pdf

latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 μF typical) located across the supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up occurring increases with increasing temperature (?) and supply voltage.

Don't know if it the same for phenom. don't know the solution AMD uses to reduce latch-up.

[bingo13]

bingo13, Which MSI board let you run 1066 divider?

The K9A Platinum, just with the latest engineering BIOS, should be public shortly.

[bingo13]

@bingo13...............if I were to opt to get one of these chips would you say the 9600 is the better move?

After today, I would say the 9600BE is the only choice, although my 9900 is running very well.

[JumpingJack]

Don't know if it the same for phenom. don't know the solution AMD uses to reduce latch-up.

SOI.

[JumpingJack]

Do you know the spec's for ram voltages on K10? I can not find that info on the amd website.
EDIT: #72
Anyway i would not try to get a b3 this way. If we ever need a quadcore workstation at work I can but my well tested one in that machine and the new one will end up in my machine for further testing.

Actually, this is a good question ... I do not know what the upper limit is spec'ed for the Phenom on the IMC, I have not looked through their specs. I can go look it up. EDIT: it is not listed, http://www.amd.com/us-en/Processors/..._15343,00.html

Nor is there a link from thier product page: http://www.amd.com/us-en/Processors/..._15331,00.html

Though, I have had a blown AMD processor in the past that they rejected the RMA for overclocking (which I did not overclock, I was not happy).

[saaya]

@BadNizze & Lightman: 9500 needs more time.

why would a 9500 need more time than a 9600? that doesnt make any sense...
It sounds more like some cpus die quicker than others...

I killed these CPUs on both the MSI and Gigabyte boards.

so first you killed it on one and then you killed it again on another board? ^^ hehehe

1.344V or so on the CPU, 2.38~2.42V on the memory voltage, NB speed around 2000, and the key it appears is that I was using the 1066 setting and clocking up from that point. This has occurred with a couple of other people. AMD is looking at one of the dead CPUs at this time, but they continue to advise us not to run memory voltages above 2.2V for any length of time.

is this 2.2v vdimm max official or unofficial?

The good news is my 0744 9600 has not died after a week of trying to kill it, but I have noticed a little degradation in memory performance now. It could be I had a couple of weaker than normal CPUs (understand the last production batch is really strong). The main reason for the potential kill problem is something we will discuss shortly.

http://www.jedec.org/

Memory is kinda loosey goosey ... there is a consortium organization, whose membership of course includes most all the major memory makers as well as Intel, AMD, nVidia etc. You can find the JEDEC standards for DDR2 memory at that web site.

The voltage for JEDEC standardized DDR2 is 1.8+/-0.1 Volts for DDR2-800, as I recall (and I may be wrong), JEDEC never ratified any specs for memory above this speed... for DDR2 anyway.

Anand has summarized the JEDEC specs for DDR2/DDR3 in this article:
http://www.anandtech.com/printarticle.aspx?i=2989

This of course does not stop memory makers from trying to woowooo your wallet with promises of faster memory or lower latency but outside of the standards -- you will commonly find low latency DDR2 but speced out at 2.0 or higher volts (operating voltage). nVidia even skirts this by the SPD to store special 'overclocked' settings for the memory used in it's SLI certified memory brand.

Nonetheless, Phenom, with the IMC, was likely built to withstand x% above and beyond the JEDEC spec, however it appears that limit is at or below 2.2 volts... so if you are looking for 1067 memory, or even low latency DDR2-800 ... pay attention to the voltage spec.

i would rather say jedec is extremely slow at doing anything at all and they are sucking up so much to everybody they cannot possibly agree on anything usefull as somebody might not like it. hence jedec specs and what mfgs and customers are REALLY running their memory at are moving further away from each other day by day. thanks to jedec not getting their job done we now have epp, xmp and amds version of epp/xmp... hooray!

and all this because jedec couldnt agree to implement a voltage option in the spd spec. cause in the end thats all epp xmp and amds epp/xmp are about. they enable high speed memory by allowing higher vdimm than default.

I believe this is related to CMOS latch-up. Then I think that the circuit design to protect from latch-up increase the input capacitance (and then reduce frequency response). I think phenom work well with low voltage memory because they have reduce protection and then associate parasitics. The drawback is you have to respect absolute maximum ratings.

wha?

Though, I have had a blown AMD processor in the past that they rejected the RMA for overclocking (which I did not overclock, I was not happy).

unless you mentioned you oced it or the cpu had clear signs from ocing thats very very unlikely. i worked for amd tech support and i cant imagine rmas being refused because of "ocing" when the cpu had never been oced or overvolted.

[saaya]

bump... so no more dead phenoms from high vdimm?
i guess there was just some ES series that had problems with high vdimm?

[Lightman]

bump... so no more dead phenoms from high vdimm?
i guess there was just some ES series that had problems with high vdimm?

Mine is still alive and kicking

[bingo13]

bump... so no more dead phenoms from high vdimm?
i guess there was just some ES series that had problems with high vdimm?

Mine were retail units, all 0743, have not been able to kill a 0744 yet, but have noticed a little degradation in memory performance.

[dinos22]

Gary how many did you kill and how are you killing them exactly
please share the settings

[saaya]

any updates?

what do you mean with memory perf degradation?
how much?

[AlabamaCajun]

I don't know exactly how it's design for a cpu, and I 'm not enough aware of cmos device. I've seen different way to reduce latch-up with circuits solutions and/or technological solutions. But I only know I've seen this kind of problem with a cmos amplifier:
http://focus.ti.com/lit/ds/symlink/tlc2652a.pdf



Don't know if it the same for phenom. don't know the solution AMD uses to reduce latch-up.

From what AMD told Bongo13, the problem appears to be current related, not substrate differential. This is evident by the fact they said any extended length of time. There is also the situation of it ocurring when clocked up which is heat build up. Look back to to page 2 http://www.xtremesystems.org/forums/...8&postcount=36 where I gave a simplified example of the current curve as the result of voltage increases.

[MR.Q]

2.4 vdimm here since day 1 (Nov 21st) no problems at all. I have decent cooling and low ambient, perhaps this helps.

[KTE]

From what AMD told Bongo13, the problem appears to be current related, not substrate differential.

Same as what I know.

2.4 vdimm here since day 1 (Nov 21st) no problems at all. I have decent cooling and low ambient, perhaps this helps.

VCore?

[JumpingJack]

unless you mentioned you oced it or the cpu had clear signs from ocing thats very very unlikely. i worked for amd tech support and i cant imagine rmas being refused because of "ocing" when the cpu had never been oced or overvolted.

The failure modes for a processor overclocked via overvolted are very easy to spot as Intel/AMD both characterize very carefully what an overvolt on the CPU will do to cause damage.

I have had a CPU RMA rejected because it was 'overvolted' in the past....

[saaya]

sorry but it sounds like for most k10 cpus 2.4v vdimm seems to be no problem... and besides benching i cant imagine why anybody would use more volts, so just like the tlb bug i dont think this is a serious issue. but im looking forward to hear how well k10 can take 2.7v vdimm from some extreme guys

I have had a CPU RMA rejected because it was 'overvolted' in the past....

so it WAS overvolted?

[Pianist]

sorry but it sounds like for most k10 cpus 2.4v vdimm seems to be no problem... and besides benching i cant imagine why anybody would use more volts, so just like the tlb bug i dont think this is a serious issue. but im looking forward to hear how well k10 can take 2.7v vdimm from some extreme guys

so it WAS overvolted?

I want to use more volts because my ram is rated to run at 4-4-4-12 1066 @ 2.4V Im scared to move it above stock now and its running at 5-5-5-18 I think. My phenom is stable at 2.6ghz with a HTT of 237 (damn wall lol), but id like to fix my timings.

[KTE]

Pianist if your RAM is rated/warrantied for 2.4V, then you might as well run it.. as long as you keep it within spec.

Can you run 1066?

[saaya]

pianist, you might not need 2.4v for 1066 444... if it runs fine with 2.3v your putting less stress on the mem and cpu, give it a try

i thought about this again and again... could it be that the nb voltage has something to do with this? maybe high vdimm low nb voltage is what actually damaged the imc? or maybe high nb voltage plus high vdimm?

[AlabamaCajun]

2.4 vdimm here since day 1 (Nov 21st) no problems at all. I have decent cooling and low ambient, perhaps this helps.

Yes, what VCore and other overvolts are you using. It's possible to reduce the stress but will it eventually give up the smoke?

[saaya]

dont think so... atm it looks rather like most of them will work fine but some cpus will under some conditions die or get damaged