Quote Originally Posted by KTE View Post
Can someone who believes in this try to explain it with some technically sound knowledge? It makes little sense to me, if I look to the physics involved unless we're missing something crucial, in which case I want to know what it is.
I believe this is related to CMOS latch-up. Then I think that the circuit design to protect from latch-up increase the input capacitance (and then reduce frequency response). I think phenom work well with low voltage memory because they have reduce protection and then associate parasitics. The drawback is you have to respect absolute maximum ratings.