High memory voltage on Phenom...

[nemrod]

I don't know exactly how it's design for a cpu, and I 'm not enough aware of cmos device. I've seen different way to reduce latch-up with circuits solutions and/or technological solutions. But I only know I've seen this kind of problem with a cmos amplifier:
http://focus.ti.com/lit/ds/symlink/tlc2652a.pdf

latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 μF typical) located across the supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up occurring increases with increasing temperature (?) and supply voltage.

Don't know if it the same for phenom. don't know the solution AMD uses to reduce latch-up.