FINALLY! Barcelona(s) + Asus L1N64......

[informal]

Additional information to access it with WPCEDIT

With 2 processor there are 2 register need to be edit :-

1) Processor node 0 = Bus#0 Device#24 Function#3 (For processor number 1)
Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

2) Processor node 1 = Bus#0 Device#24 Function#3 (For processor number 2)
Offset D4h (32bit access mode) , Bit 0,1,2,3,4 (5bit)

NB clock = 200 x (NbFid + 4).
*NBFid = in decimal


Bit = Hex = Decimal = NB Speed calculation
00001b = 1h = 1 = NB clock 200x (1+4) = 1000MHz
00010b = 2h = 2 = NB clock 200x (2+4) = 1200MHz
00011b = 3h = 3 = NB clock 200x (3+4) = 1400MHz
00100b = 4h = 4 = NB clock 200x (4+4) = 1600MHz
00101b = 5h = 5 = NB clock 200x (5+4) = 1800MHz
00111b = 6h = 6 = NB clock 200x (6+4) = 2000MHz
....
11011 = 1Bh = 27 = NB clock 200x (27+4) = 6200MHz

Thanks for this info tictac
I wanted to ask you if you know anyone who was able to run Barcelona/Phenom (be it retail or ES) with NB clock greater than 2GHz?Since according to your posting,the chips are able to run the IMC/L3(both inside the NB domain) at a far greater frequencies(6.4Ghz,in theory) of those 1.6/1.8Ghz we saw in tests up to now...
I suspect the ~2.5Ghz NB clock could greatly help reduce the L3 latency as well as mem. latency!And we know AMD uses the same sram for L2 and L3 and we know they are able to clock them as high as 3.2Ghz on 6400+ case and as up to 2.7 revG2(and presumably the 2.9Ghz as yet unreleased G2 part will work at).Since the L2 in these K8s is the same type of cache AMD used for the L3 in K10,there should be no reason this L3 couldn't work on ~2.5Ghz-like clocks.