Quote Originally Posted by s7e9h3n View Post
Kyosen-san, are you running a single 2gb stick of memory?
No, I'm running my board with 1GB Reg. memory modules.
I tried 2x 2350 and 4x = 2x + 2x memory modules in this morinng.
My 1GB modules is 1 rank(bank) type, so it looks that bank-interleave is disabled,
but all 4x modules are detected and working:
http://www.oohashi.jp/images/L1N64_K10_x2_memory_x4.png

And here, additional explanation of register mod with MchbarEdit...
...instead of private mail...it's convinient, I think

HT Link multiplier
Target registers are F0x[0E8,0C8,0A8,088].
Barcelona/K10 is designed to have 4 HT Link,
but it looks that one of them is disabled for current K10 Opteron...
...in this case, F0x0E8 is reserved for 4th HT Link, and it's disabled now.
Then, we can observe the value like 80750660 on F0x[0C8,0A8,088] with MchbarEdit.
From AMD's BIOS and Kernel Developer's Guide, Page 146,
HT Link is set as below:
80750660 = x5
80750560 = x4
80750460 = x3
80750360 = reserved (...probably x2.5!? not tested)
80750260 = x2
80750160 = reservied (...probably x1.5!? not tested)
80750060 = x1
We can write desirable value on it, and after rebooting, it should be changed.
# Also we should be able to change HT Link width 8bit/16bit with registers mod
# for F0x[0C4,0A4,084] in similar way, but I've not tested it.

North Bridge multiplier
Target register is F3x0D4.
We can observe the value like C331F024 on F3x0D4 with MchbarEdit,
and last digit (4 in the above case) is NbFid, i.e. NorthBridge Frequency ID.
NB clock is defined as "200 x (NbFid + 4) / (2^NbDid)"
NbDid, i.e. NorthBridge Divisor ID is defined at MSRC001_00[68:64], and it's 0 in default.
2^0=1, so we can think simply NB clock = 200 x (NbFid + 4).
We need to reboot to give effect to changing F3x0D4[NbFid].
# Oppositely, NbDid is changeable without reboot, so the system can reduce NB clock dynamically.