Here's a little teaser....

[dave_graham]

gotta love it.

dave

[dinos22]

Ugh, this poor system. The memory is just being abused just to get it to run. The timings are auto, which of course are bad, then for some reason it's in single channel mode, at 266MHz, and the HT Link is slow as Hell. Yikes is all I can say. Here's a painfully slow SuperPI 1M for what it's worth. Gotta get back to work.



Ninja Edit: The first bank of memory (first four sticks) are the only ones showing up. The other 4 sticks in the bank next to CPU #2 aren't showing up at all, so it's only seeing 8GB of memory (but this is 32-bit Windows, so it doesn't really matter). However, the memory is still showing up in slots 1/2/3/4, so I'm not sure why dual channel isn't kicking in...

Spi for the guy that cannot find it heheheh

[tsuehpsyde]

Now we are 100% sure something funky is going on with all 3 rigs in question here .

Yeah, I was hoping to see it boot up at DDR2-667 on the other machine, but the BSOD said no dice. Oh well, hopefully s7 and Dave have better luck than me.

[freeloader]

It would appear that none of these board manufacturers should put a "Quadcore ready" sticker on their boxes! Perhaps a sticker that should read, "Not quite ready for Quadcore yet" would be more appropiate

Of course I'm sure in a couple of weeks/months they'll have things figured out.

[bigdaddy25fb]

It seems to be BIOS issues...

[KTE]

Thanks tsuehpsyde. That score shows exactly what I was thinking - problems with cores communicating. Cache-2-Cache would help here but I doubt it runs in Windows.

The biggest advantage of the K10 over Core 2, its L3 cache, memory bandwidth, Crossbar, HT links and IMC is supposed to show up in all this where Intel is touted as FSB/NB being the bottleneck.
If you were to believe those results as conclusive, it would seems the L3/IMC/HT are the bottleneck and AMD needs desperately to move to the FSB/large L2 ASAP!

That's just far lower than what you could expect with 2x 2400MHz K8s, that get around 90ns latency and 5200MB/s averaging until 64x 8KB, where they get 3000MB/s thereafter, mainly due to a lack of shared L2 cache.

2x Xeon QC 2400MHz gets a peak of 43350MB/s for quite a while during those tests before it drops to around 5000MB/s late at the end. Me thinks the test is very L2 cache size dependent.

Can any of you guys ask your AMD contacts/reps if any of those results are OK/decent or off the mark? They should know for sure how good it "possibly" is, if much..

[s7e9h3n]

L3 cache decreases the latency between the IMC and the memory

[JohannesRS]

Please God say it's only the bios....

[PhilDoc]

Its only the bios, but the latentcy of the l3 is a little bit of an issure from what I've read. The communication between the cores is also suppose to be an advantage.

[JohannesRS]

anyway...

it's interesting. Dave and S7 could give better info on this, but I THINK that there weren't so many issues in the transiton from single to dual core opterons, am I right?

That would lead to the conclusion that the problem with this is coming not exactly from the quad-core feature, but from the K10 plattaform itself. In terms of compability of bios, of course, but it's not the number of cores that is the issue.

And that last move would lead to one of the discussions I've read about the problems AMD got: it's worst mistake was to try to push at the same time 65nm, K10 and quad-core. Of course, they had no other option, specially when the initial project from K8Ls were down (if this rumour is true, of course). But it seems that the price of pushing everything at the very same time is still being paid...

[BeardyMan]

Mate stop being so close minded.

K10 is the main arch, most that AMD can do on phenom to improove performance (IPC) is to increase the mem controler speed and that is it.

I'm not your mate

and phenom will be different vs this current processor, launch clocks, launch date should say enough nuf said

btw your interpretation was wrong.

[s7e9h3n]

anyway...

it's interesting. Dave and S7 could give better info on this, but I THINK that there weren't so many issues in the transiton from single to dual core opterons, am I right?

That would lead to the conclusion that the problem with this is coming not exactly from the quad-core feature, but from the K10 plattaform itself. In terms of compability of bios, of course, but it's not the number of cores that is the issue.

And that last move would lead to one of the discussions I've read about the problems AMD got: it's worst mistake was to try to push at the same time 65nm, K10 and quad-core. Of course, they had no other option, specially when the initial project from K8Ls were down (if this rumour is true, of course). But it seems that the price of pushing everything at the very same time is still being paid...

While you make some valid points here, IMO, the issue isn't with the die shrink or additional cores. The problem seems to lie within Barcelona's new "power-saving" features. For example: the current bioses are incorrectly identifying P-states on these chips as well as underclocking the northbridges since dual power planes have yet to be implemented. It also didn't help that AMD had issues getting fully functional procs to the mobo makers due to poor initial yields. Realistically, I think we're about a month away from seeing Barcelona running smoothly on our current platforms

[JVguest]

This is looking like a fiasco.. and judging by some benches I did on A64 2.2 GHz with 3x HTT andt 1x HTT will have a significant impact on performance, more so because my A64 was one core while barc is 4 cores. I don't know what to say about the cores entering power saving mode, but obviously that would have a dramatic effect on performance.

It's clear the mobos aren't ready.. at BEST 1 month till issues are resolved, probably 2 months before anything K10 based is available in regular retail channels.

[justapost]

I honestly think CPU-Z is telling lies about my HT Link as well.

on a s3992 with 2210 it does not report the HT speed correct (1x). CrystalCPUID does a better job (4x).

[DoubleZero]

BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors:

http://www.amd.com/us-en/assets/cont...docs/31116.pdf


Maybe this PDF can help a little.

[PhilDoc]

I just wonder how much of a mistake they made by trying to make Barcelona drop in compatable. I applaud them for doing so, but things mayb be smoother right know if they hadn't.

[KTE]

AFAIK, AMD stated "less than 38 cycles" for the L3 cache latency, and stated it's squarely dependent on the NB speeds > far quicker than going to RAM... or it's supposed to be if they all sync correctly.

I wonder if HP, Dell, IBM and Sun systems are having similar issues...

I can say one thing; during the time AMD took for releasing this, Intel worked and made up it's deficit in every other sector it was weaker on, and Penryn just adds to that further. Right now, even the FP lead by the K10 is no where near what it used to be with 1st Gen Optys, per clock basis.

Aneeeee-way.... keep up the good work fellas. I'd hate to have to mess with fixing this without any immediate benefits.

[Antinomy]

I want to say, that I've written an article about tweaking A64 memory controllers (and not only them). And about tweaking Barcelona in particular. You are welcome to read and send your feedback
But the only issue is that it bases on another article about WPCREDIT. It's on Russian at the moment. If you need it (or any other issue there), I can work on a translation.

[doompc]

Nice work, Antimony.
Are there english versions of these articles?
http://people.overclockers.ru/antinomy/record4
http://www.overclockers.ru/lab/15689.shtml

[dave_graham]

While you make some valid points here, IMO, the issue isn't with the die shrink or additional cores. The problem seems to lie within Barcelona's new "power-saving" features. For example: the current bioses are incorrectly identifying P-states on these chips as well as underclocking the northbridges since dual power planes have yet to be implemented. It also didn't help that AMD had issues getting fully functional procs to the mobo makers due to poor initial yields. Realistically, I think we're about a month away from seeing Barcelona running smoothly on our current platforms

ermmm.....I'll know in a week.

got my 3992-E on order now and am working over the powers that be to get it to me earlier.

dave

[tictac]

thats is why amd introduce ht3 for k10. the l3 cache located inside the northbridge. do you want faster northbridge speed? oc the l3 cache for good hehe

[dave_graham]

thats is why amd introduce ht3 for k10. the l3 cache located inside the northbridge. do you want faster northbridge speed? oc the l3 cache for good hehe

HT3 is present in the K10 core but fused out. there is no possible way of utilizing HT3 on the cpu.

cheers,

dave

[Brother Esau]

@DaveGraham ........Good Morning Dave whats the verdict on this ATM will Barcelona be dampered in performance on the current boards?
I really want to get away from Overclocking for a while "no time" lately because of work and life so what would be my best bet if I choose not to wait for middle or late 2008 for new board from SM a Dual Dual socket F or what?

[tictac]

HT3 is present in the K10 core but fused out. there is no possible way of utilizing HT3 on the cpu.

cheers,

dave

ok... but we still can speed up the LDT Frequency? to increase L3 cache performance right?

[Lightman]

ok... but we still can speed up the LDT Frequency? to increase L3 cache performance right?

At least Phenom will have HT3.0 enabled. Hope that motherboards will provide options to clock NB and L3, that will be nice .