Barcelona Launch Clock Speeds Changing?

[Donnie27]

I don't know anything about Smart L2 and SMA, but you know... Intel's L2 and L3 cache latencies are very little. L2 has a latency of around 12 and their L3 has a latency of 14....... AMD's L2 has a latency of 18... and their L3 has a latency of around 30-40 something from what I've heard. I admit, I'm an intel fanboy, but even I would like to see atleast competing barcelona scores for benchmarks. I'm actually hoping all of these benchmarks, the superpi especially, is fake. 39 second 1mb is bad... my PD could beat that, but in all reality, AMD's chip doesn't sound very impressive, and the cache sizes and latencies would probably explain the super pi score. AMD's chips may have more L1, but they really can't compete against 8mb-12mb of 12 lat L2 cache....

Current Intel Processors doesn't use an L3. SO if you meant L1 and L2, sure. It's kind of hard to talk to these guys when they put their love for AMD in front of common sense. I've seen AMD Fans call other AMD Fans Intel fans because they didn't repeat AMD's spin.

Now since Intel's and AMD architectures are different, Cache dependence, the Amount of Cache and even the way the cache is setup (Inclusive-Exclusive) is different for each company as well. I believe each is using what's best for them. Small fast is good for Intel just as a larger L1 is better for AMD. Intel tried L3 and got mixed results on the desktop. Another example, read up on L1/L2 cache ECC or error correction and tell me if you still think AMD's way is the best way to do it?

K10 will not only need a smarter Pre-Fetch as the other guys mistakenly still don't get. Even after linking these same 3 Hardcore AMD fans to what Smart Cache and Smart Memory access was, they still didn't get it. It will matter for K10 as well if AMD doesn't improve on its Dumb Memory Access, K10 will not Gain that much. Meanwhile how blocks of memory is stored, how that stored memory is accessed and even the speed of access will only get better for Intel.