Quote Originally Posted by savantu View Post
Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.
L2 is still twice faster than memory.
Also it has some smart prefetch.

Is there any such test showing how much performance would degrade with L1 and L3 enabled for other chips that already on market?

And finally, why K10 having lots of improvments against K8 shows exactly same performance per core? Where is 15% over K8???