Quote Originally Posted by SEA View Post
If L2 disabled but L3 is enabled - this will change things from slideshow significantly.
Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.