K10 Scores starting to surface

[Mad_Man]

Bus speed is the HTT. HT is different than the bus speed/FSB/HTT.

i was talking about this:
cpuz 1.41 should be barcelona compatible, if i can call it that.
so cpu-z should show bus speed as 200mhz, and HT link 1000mhz for stock system??

[Sparky]

Shouldn't CPUZ show "HT Link" link instead of "Rated FSB" like usual AMD cpus? If the HT link is actually running at 200 instead of 1000+, this would be a huge bottleneck as Mad Man said.

Should, don't know why it says FSB since AMD doesn't use a FSB. Should have the bus speed (the HTT, has been 200MHz on K8) and the HT link (1000MHz on K8). Tells me that CPU-Z still doesn't detect K10 properly.
Unless that is a fake screenshot, with an intel chip in there and things mspainted or something like that

[terrace215]

Isn't it very convinient this info comes from the intel exclusive place(coolaler forums),and that it is coming only a day after Theo's post??It could be that Theo's results were in some way inflated(since the score is really hard to believe),but this avalanche of "poor K10 results" comes after he wrote this:

Conspiracy theories? The results fit with AMD's OWN DOCUMENTS on K10 performance vs. K8. Why can't you accept that AMD knows how the K10 performs?

Don't tell me you listened to the non-technical hype from Pat Patla and the now-fleeing Henri Richard?

[SEA]

...
And try to disable L2 - you will see slide show instead of your windows

If L2 disabled but L3 is enabled - this will change things from slideshow significantly.

[informal]

Conspiracy theories? The results fit with AMD's OWN DOCUMENTS on K10 performance vs. K8. Why can't you accept that AMD knows how the K10 performs?

Don't tell me you listened to the non-technical hype from Pat Patla and the now-fleeing Henri Richard?

Lmao.With all the NDAs around,somehow Sun's got leaked and spilled out the all hush hush about K10 performance and summed it up to poor "up to 15% IPC improvement"

Can you post anything positive about AMD,ever?

[savantu]

If L2 disabled but L3 is enabled - this will change things from slideshow significantly.

Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.

[savantu]

Lmao.With all the NDAs around,somehow Sun's got leaked and spilled out the all hush hush about K10 performance and summed it up to poor "up to 15% IPC improvement"

Can you post anything positive about AMD,ever?

I have the same number from a Cray presentation ; 15% better IPC ( that is for HPC code , which K8/10 likes most ) + extra % due to higher clock ( didn't happen ).

Can you post something anything true about AMD , ever ?

[Sparky]

Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.

Reality is this:
You, nor I, nor most people here know enough to say for certain how the chip is going to perform. We have conflicting benchmarks from different sources. Just wait until after Sept. 10th and then we'll know for sure.

And no reason to be calling people idiots just gonna raise tempers and not do any good. Geeez why can't people be respectful enough of each other to refrain from name-calling....

[SEA]

Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.

L2 is still twice faster than memory.
Also it has some smart prefetch.

Is there any such test showing how much performance would degrade with L1 and L3 enabled for other chips that already on market?

And finally, why K10 having lots of improvments against K8 shows exactly same performance per core? Where is 15% over K8???

[kl0012]

Oh sure , the magic 38 cycle latency L3 will come to the rescue.

Sorry , but only an idiot could believe any of the caches or execution units to be disabled when the chip performs +/- 10% of C2D.

Reality is this : the chip is perfectly fine, but it's "bugs" prevent it from scaling , that is reaching higher clockspeed while maintaining data integrity.In other words ; you're fine at 2GHz , but at 2.3GHz* due to speedpath problems you get silent data corruption or other nasty surprises.

* Example.

+1
I don't understand why ppl thinks that it must be faster then C2D/C2Q in non-bandwidth dependent aplications.

[red]

If L2 disabled but L3 is enabled - this will change things from slideshow significantly.

http://www.xtremesystems.org/forums/...&postcount=173

the benches are from a 2 socket opteron socket and as additional info the memory is running 667 speeds cas5. what superpi perfromance do you expect.
the performance can't be compared with the phenom. try to bench a k8 with memory 667 cas5 and then change it to 1066 cas5 like the demo system AMD is showing. even at the same speed it will be a huge performance difference.

looking and comparing the cpu-z from Coolaler to mine it is a fact that his sample is a dvt or early bird from oem. so it will be the chip that launches within a few days. All features are enabled, K10 is no INT miracle it will be as fast as core and no penryn is not faster then conroe, it's just when the program is affected by cache or not it will be faster clock/clock and the magic sse4. k10 will increase the gap on fpu and IO even more not to mention virtualization. How well it scales will be depending on the new stepping coming in oktober and you'll see how well it does when people get phenom es in there hands.

informal's information about the bios is correct, it is changing alot, systems with b0 had no CPU options in BIOS available except changing HT speed.

The chips aren't bugged??? it's the BIOS at worst. Or maybe this is K10 performing at its best lol

[kl0012]

And finally, why K10 having lots of improvments against K8 shows exactly same performance per core?

Actualy it is faster than K8 per core (if these tests are true).

[informal]

Actualy it is faster than K8 per core (if these tests are true).

Yeah the whole 3-8%.

[SEA]

Actualy it is faster than K8 per core (if these tests are true).

Actually it is within 4% difference for me.
Need screeny?

[Donnie27]

there are details that are still missing here...what motherboard(chipset), what ddr2 ecc single or dual channel? etc...
a lot of people giving opinions but what's the platform that this was tested...

So why were folks being flamed for suggesting old boards would suck with new processors? So, why bother with all of the BS about Socket Continuity? Guys, you can't have it both ways. It's either great with old boards and it's all good or its only so so and a new board is needed anyway. Ibet a new board is needed.

Rumor! A guy in Germany told me one tester is running Penryn on an i865, I told him I'd believe it when I see it. Yet, I wouldn't touch that setup with AGP, SATA1 and all of yester-year's tech. In fact, I'm already wanting to upgrade my GA-965 DS3.

[kl0012]

Yeah the whole 3-8%.

I doubt we can expect more in non-SSE2-vectorized aplications. As was said before it is only up to 15% IPC improvements.

[Hornet331]

Rumor! A guy in Germany told me one tester is running Penryn on an i865, I told him I'd believe it when I see it. Yet, I wouldn't touch that setup with AGP, SATA1 and all of yester-year's tech. In fact, I'm already wanting to upgrade my GA-965 DS3.

Same here.

whatever is out in Nov-Dec and is the fastest, I'll buy.

[PetNorth]

Actualy it is faster than K8 per core (if these tests are true).

not really. In Cinebench is exactly the same, what doesn't make any sense, keeping in mine K10 improvements.

[jabway]

not really. In Cinebench is exactly the same, what doesn't make any sense, keeping in mine K10 improvements.

Somehow the massive core improvements amount to a 3-4% increase against K8.

Doesn't make any sense at all.

[Nedjo]

What's to laugh about ?

Have you heard of Fusion , Silverthorne ?

The purpose of such devices is to move the PC as we know it on the cellphone. Current cellphones are slowly going uphill into PC territory ; this will advance at a very rapid pace once system-on-a-chip devices appear next year.The whole point is to move x86 down , into cellphone territory and this is the purpose of Silverthorne early next year. ( Iphone 2 will use it according to rumours )

This is real and is happening now ; both Intel and AMD are preparing for the 2010-2012 generation , by that time , cell phones will be more powerfull than current PCs.Add 3D glasses to them and all my multimedia needs are satisfied.

/End off topic.

so you're SUN guy:
http://www.dailytech.com/article.aspx?newsid=8658

[uOpt]

not really. In Cinebench is exactly the same, what doesn't make any sense, keeping in mine K10 improvements.

The numbers are about 7% better per-core with the clockspeed normalized.

[PetNorth]

No, like I said before, I've run my X2 at 2.0ghz (with cinebench 10 x64), and 1cpu result was 1905 (1896 this K10).

[Donnie27]

Same here.

whatever is out in Nov-Dec and is the fastest, I'll buy.

Doesn't matter, I can be hungrey for and buy the Phenom X4. According to some in this thread, I'd still be called an Intel Fanboy LOL!

[JVguest]

I have the same number from a Cray presentation ; 15% better IPC ( that is for HPC code , which K8/10 likes most ) + extra % due to higher clock ( didn't happen ).

Can you post something anything true about AMD , ever ?

I can believe K10 would run rings around K8 at same clock. The mere doubling of SSE throughput means that a lot of HPC apps will run near twice as fast. Core 2 is in many cases near twice as fast as P4 clock for clock
in HPC is some cases up to 4 times as fast.
The 32 byte fetch means K10 should be a floating point monster (HPC).The load forwarding capabilities of K8 are quite deficient (none!) compared to Core 2 ( load forwarding already in pentium pro) which means that their inclusion in K10 will give an even bigger boost than Core 2 got from it. Too bad the clock rate is low and the cache is relatively small.

[kl0012]

The 32 byte fetch means K10 should be a floating point monster (HPC).

32 byte fetch can help with decoding long instructions, but K10 still limited by 3 x pipeline (Core has 4 x pipeline). It can't help in legacy code with short instructions.
But Core(tm) feature 64-byte fetch buffer wich can help short loops run faster (on any code).

The load forwarding capabilities of K8 are quite deficient (none!) compared to Core 2 ( load forwarding already in pentium pro) which means that their inclusion in K10 will give an even bigger boost than Core 2 got from it. Too bad the clock rate is low and the cache is relatively small.

Core(tm) is still better in almost all which is related to the memory subsytem.

http://www.xbitlabs.com/articles/cpu...k10.html#sect0

As a result, we see that the memory subsystem of K10 processors has undergone some positive improvements. But we still have to say that it still potentially yields to the memory subsystem in Intel processors in some characteristics. Among these features are: the absence of speculative loading at unknown address past the write operations, lower L1D cache associativity, narrower bus between L1 and L2 caches (in terms of data transfer rate), smaller L2 cache and simpler prefetch. Despite all the improvements, Core 2 prefetch is potentially more powerful than K10 prefetch. For example, K10 has no prefetch at instruction addresses so that we could keeps track of individual instructions, as well as no prefetch from L2 to L1 that could hide L2 latency efficiently enough. These factors can have different effects on various applications, but in most cases they will determine higher performance of Intel processors.