Quote Originally Posted by largon View Post
Link?
If this were true...
I went to the Barcelona presentation and asked directly to the presenter about this. He confirmed the integer divider limitations were solved.

I'm prety sure we'll have 1MHz step memory clock adjustment all the way up to about 750MHz (DDR2-1400).

Also, the IMC received a deep upgrade (larger write bufer, dual channel is now two independent 64bit channels, DDR2-1066 official support, the data path to the northbridge was extended to 128 bits, and so on).

30k still seems unreal, but I think it will be at least 10% faster per clock than Penryn in general application, and way more in highly multithreaded workloads.