Official Desktop Penryn Discussion Thread

[informal]

Says who ?

http://www.theinquirer.net/default.aspx?article=38232

[savantu]

http://www.theinquirer.net/default.aspx?article=38232

I've read that months ago.

Since Nehalem hasn't even taped out , I would take the usual spoon of salt with the Inq article.

The FSB is simply out of breathing room and I doubt Intel will use a CSI link as a FSB , simply doesn't sound rigth.

[Shadowmage]

I've read that months ago.

Since Nehalem hasn't even taped out , I would take the usual spoon of salt with the Inq article.

The FSB is simply out of breathing room and I doubt Intel will use a CSI link as a FSB , simply doesn't sound rigth.

That looks like a good article.

Given that Intel's design cycle is 5 years long, what could you possibly mean by the "since Nehalem hasn't even taped out" argument? Don't you think that the design would have been close to finalized BEFORE it has been taped out?

In the graphics card realm, the design cycles are much shorter, and the competition much fiercer, so there's a lot of misinformation spewed all the time. However, I really can't think of any time TheInq has been wrong about CPU specification information (not clock speed information... specification information).

[savantu]

That looks like a good article.

Given that Intel's design cycle is 5 years long, what could you possibly mean by the "since Nehalem hasn't even taped out" argument? Don't you think that the design would have been close to finalized BEFORE it has been taped out?

In the graphics card realm, the design cycles are much shorter, and the competition much fiercer, so there's a lot of misinformation spewed all the time. However, I really can't think of any time TheInq has been wrong about CPU specification information (not clock speed information... specification information).

Intel's design cycle is 4 years old.

Secondly Nehalem was designed to be completly modular , you can modify it much easily than older designs , that is you don't have to redo everything.
With this extra flexibility Intel can choose between IMC or not , integrated graphics or not , etc.

What I mean is this : FSB is out of breathing room ; you can't go over 1600MHz with ease , the technicals hurdles are staggering and the law of diminishing returns kicks in.

While it might be fine for notebooks , on desktops once the core count reaches 4 and above the limitations start to pan out.

[Donnie27]

http://www.theinquirer.net/default.aspx?article=38232

Instead of a Grain-of-Salt, take that one with a whole damned teaspoon

Example---->The volume part, Thurley, will have three DDR3 channels per socket. The memory is currently slated to run at 800/1066/1333, so bandwidth will not be a problem there. We understand Intel is adopting the micro-buffer strategy from AMD. As we say here in Arkansas, "that's Hog wash". Intel, just like AMD used Alpha for inspiration.

Core doesn't need an integrated memory controller simply because it's not memory bandwidth starved. Test it with crappy RAM and that will become blatantly obvious.

Secondly Nehalem was designed to be completly modular , you can modify it much easily than older designs , that is you don't have to redo everything. With this extra flexibility Intel can choose between IMC or not , integrated graphics or not , etc.

Absolutely QFT!

[Donnie27]

Nehalem is also NOT just another Core 2 like Penryn and might actually make use of an IMC. Otherwise, it becomes just a Gimmick. Also, it'd be pretty stupid IMHO, if Intel added all higher end tech on all processors, even the budget models. I THINK Intel will do just like they did with Hyperthreading (HTT makes a return on Nehalem) and split the line-up feature wise.

[Shadowmage]

Intel's design cycle is 4 years old.

No, it's 5 years.

Secondly Nehalem was designed to be completly modular , you can modify it much easily than older designs , that is you don't have to redo everything.
With this extra flexibility Intel can choose between IMC or not , integrated graphics or not , etc.

That's true, but all the performance data for with/without IMC and such take months to complete. Most of this stuff will have been decided many months in advance.

What I mean is this : FSB is out of breathing room ; you can't go over 1600MHz with ease , the technicals hurdles are staggering and the law of diminishing returns kicks in.

While it might be fine for notebooks , on desktops once the core count reaches 4 and above the limitations start to pan out.

That's true. That's why they're switching to CSI.

[Shadowmage]

Example---->The volume part, Thurley, will have three DDR3 channels per socket. The memory is currently slated to run at 800/1066/1333, so bandwidth will not be a problem there. We understand Intel is adopting the micro-buffer strategy from AMD. As we say here in Arkansas, "that's Hog wash". Intel, just like AMD used Alpha for inspiration.

Why is that "hogwash"? TheInq's speculation may be incorrect but the data about Thurley is certainly believable, especially since many other sites have confirmed it.

Core doesn't need an integrated memory controller simply because it's not memory bandwidth starved. Test it with crappy RAM and that will become blatantly obvious.

That's half true. Core has plenty of memory BANDWIDTH but still suffers from high memory LATENCY.

Also, it'd be pretty stupid IMHO, if Intel added all higher end tech on all processors, even the budget models. I THINK Intel will do just like they did with Hyperthreading (HTT makes a return on Nehalem) and split the line-up feature wise.

That's true, but the problem is that only the XE editions will get the IMC. Even the high-end desktop parts will not have an IMC.

[informal]

That's true, but the problem is that only the XE editions will get the IMC. Even the high-end desktop parts will not have an IMC.

Yeah,that's what i think also.

[Donnie27]

Why is that "hogwash"? TheInq's speculation may be incorrect but the data about Thurley is certainly believable, especially since many other sites have confirmed it.

I'm not talking about TheInq, I'm talking about folks testing and saying as much. I find that MaximumPC, Tech Report, ExtremeTech, and many others who tested slow RAM know what they're talking about. No site confirm RAM making more than 2 or 3% difference with Core2 Duo or even Core 2 Quad=P A64 can be affected buy slower and higher latency RAM, that just not true for Core=P

That's half true. Core has plenty of memory BANDWIDTH but still suffers from high memory LATENCY.

Absolutely not, especially compared to the hit Athlons on AM2 takes with an IMC and slower RAM. Core features a Smart L2 and Smart Memory Access. Each of these are tweaked and improved even more on Penryn. These make the use of an IMC moot. Please note, for single sockets, it also nullifies the negative effects of the FSB.

Latency

Nehalem will use SMT and might need an IMC, just as more than one socket will benefit from CSI.That's where CSI will prove more valuable.

That's true, but the problem is that only the XE editions will get the IMC. Even the high-end desktop parts will not have an IMC.

NO ONE knows who'll get IMC but CSI is just what it is. Note the first letter? C is for Common in this case.

Please don't contradict yourself. XE is the high end and everything else will be mainstream. Even without an IMC, these babies will kick mucho ass just as they are with even higher latency DDR3 running at 1333 and 1600MHz.

[Donnie27]

Yeah,that's what i think also.

Then you're off as well.

[Donnie27]

Added. It's "Hog Wash" because AMD and Intel used Alpha for a lot of ideas. Intel had working Timna with an IMC before any Athlon with it shipped.

[Shintai]

Added. It's "Hog Wash" because AMD and Intel used Alpha for a lot of ideas. Intel had working Timna with an IMC before any Athlon with it shipped.

Intel also had working 386SL and 486SL with IMCs before

[savantu]

No, it's 5 years.

...

It's 4.

Pleas do tell what design has taken Intel 5 years to complete. ( except Montecito which was delayed by 1 year due to implementation issues )

[savantu]

...

That's true, but the problem is that only the XE editions will get the IMC. Even the high-end desktop parts will not have an IMC.

That would mean different boards for the XE series.I really doubt Intel will do such a thing.

[dexman]

That would mean different boards for the XE series.I really doubt Intel will do such a thing.

why not? it makes sense. XEs would work with boards based on only high-end chipset.

[savantu]

why not? it makes sense. XEs would work with boards based on only high-end chipset.

No it doesn't.

Intel's strength derives from its manufacturing excellence.

What's the MS for XE edition ? 0.01% ?

Does that warrant the following :

1.Different mask.
2.Mobos
3.Chipset.
4.Validation time.

The answer is obviously no.IMO , Intel would be pretty stupid to do that.

[dexman]

No it doesn't.What's the MS for XE edition ? 0.01%?

And that´s the very good reason to do something about it. Many people can´t justify buying XEs. Too pricy and you can have same results with overclocked Exxxx models. Heck, some of them oc even better than XEs.

Lets say Intel drop prices on XEs and introduces more of them, not just one - the highest clocked cpu. Kinda like all CPUs over 3 GHz are XE while highest clocker is still priced very high. They separate them from others by better features (CSI, better oc chipset, etc...), that way XE would still hold upper hand over regular model at same clocks. In the end, more people will start buying XEs and high-end chipset boards.

[Donnie27]

Intel also had working 386SL and 486SL with IMCs before

Slaps self on the head in a "Could have had a V8" fashion. Thanks!

[Jacky]

No it doesn't.

Intel's strength derives from its manufacturing excellence.

What's the MS for XE edition ? 0.01% ?

Does that warrant the following :

1.Different mask.
2.Mobos
3.Chipset.
4.Validation time.

The answer is obviously no.IMO , Intel would be pretty stupid to do that.

but maybe the extreme margins (low volumes though) on XEs would justify all the work...

[Donnie27]

And that´s the very good reason to do something about it. Many people can´t justify buying XEs. Too pricy and you can have same results with overclocked Exxxx models. Heck, some of them oc even better than XEs.

Then you have a lot of users (more of them than us BTW) who buy the top two or three models and NOT overclock. I see these folks more and more on forums all over the Web.

I'm not-well off by any means but one of the last rigs I bought before becoming a 100% DIYer cost me about $3,400 in 1995.

Lets say Intel drop prices on XEs and introduces more of them, not just one - the highest clocked cpu. Kinda like all CPUs over 3 GHz are XE while highest clocker is still priced very high. They separate them from others by better features (CSI, better oc chipset, etc...), that way XE would still hold upper hand over regular model at same clocks. In the end, more people will start buying XEs and high-end chipset boards.

I think I'll wait and see just how Intel uses CSI. My point is, IMHO, just that it is NOT that important on any Intel Single socket system=P The FSB is NOT that frackin bad for Conroe and Penryn desktops. That goes for CSI and IMC. If Nehalem is different enough, it might need an IMC though but I doubt it. IMHO, sure I could be wrong as hell, IMC and CSI becomes a Gimmick.

There's just too much negative BS propaganda IMHO about the FSB for a Single Socket system. 95% of the time, my estimation from using my E6600 stock and overclocked, even with the RAM even slowed to 667, has very little effect on my performance bandwidth wise. Latency is almost not worth talking about. The worse problem with slow RAM on a Conroe system are poor overclocking results.

[Donnie27]

No it doesn't.

Intel's strength derives from its manufacturing excellence.

What's the MS for XE edition ? 0.01% ?

Does that warrant the following :

1.Different mask.
2.Mobos
3.Chipset.
4.Validation time.

The answer is obviously no.IMO , Intel would be pretty stupid to do that.

Hell, I agree!

[T2k]

July 22 price cut confirmation and yet another price cut coming in September 2?



Source

Somebody tell me, please, how would it make sense to cut prices TWICE in SIX WEEKS?
IIRC last price cut was in late April or early May, so the upcoming July 22 markdown makes sense - but another one only 5-6 weeks later?

PS: of course, if it's only about drying up any revenue AMD still enjoys then it makes sense - but it would still hurt their own (Intel) revenues too.

[Donnie27]

Somebody tell me, please, how would it make sense to cut prices TWICE in SIX WEEKS?
IIRC last price cut was in late April or early May, so the upcoming July 22 markdown makes sense - but another one only 5-6 weeks later?

If you have a lot of faster products coming and the market is in a slowdown rut, you cut prices=P Once sales pick up, or if they pick up, prices first hold steady, then they rise. Look at RAM that's more volatile but gives an accelerated example. Notebooks and Smaller Servers are the only thing selling real well right now according to most market watchers.

[T2k]

If you have a lot of faster products coming and the market is in a slowdown rut, you cut prices=P Once sales pick up, or if they pick up, prices first hold steady, then they rise. Look at RAM that's more volatile but gives an accelerated example. Notebooks and Smaller Servers are the only thing selling real well right now according to most market watchers.

So you would even kill the sales of your just-marked-down products? Hmmm...