Quote Originally Posted by informal View Post
http://www.theinquirer.net/default.aspx?article=38232
Instead of a Grain-of-Salt, take that one with a whole damned teaspoon

Example---->The volume part, Thurley, will have three DDR3 channels per socket. The memory is currently slated to run at 800/1066/1333, so bandwidth will not be a problem there. We understand Intel is adopting the micro-buffer strategy from AMD. As we say here in Arkansas, "that's Hog wash". Intel, just like AMD used Alpha for inspiration.

Core doesn't need an integrated memory controller simply because it's not memory bandwidth starved. Test it with crappy RAM and that will become blatantly obvious.


Quote Originally Posted by savantu
Secondly Nehalem was designed to be completly modular , you can modify it much easily than older designs , that is you don't have to redo everything. With this extra flexibility Intel can choose between IMC or not , integrated graphics or not , etc.
Absolutely QFT!