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Let me help; the DRAM Skews help optimize latency between individual dimms (since they're positioned at different distances from the NB) and the NB. The following screenshots show:
Q9550 @ 8.5x475
G.Skills PC2-8500 @ 1140, 2.128v
VNB @ 1.550v
DRAM Static Read Control = Enabled
AiClock Twister = Stronger
DRAM Skews A = 250
B = 350
Last edited by Zucker2k; 10-13-2008 at 09:05 AM.
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