From the last "Intel® Core™2 Extreme Processor QX9650 and Intel® Core™2 Quad Processor Q9000 Series Specification Update"
http://www.intel.com/design/processo...pdt/318727.htm

Errata AV51

AV51. Front Side Bus GTLREF Margin Results Are Reduced for Die-to-Die
Data Transfers in Intel® Core™2 Extreme Processor QX9650, Which
Can Lead to Unpredictable System Behavior

Problem: In a synthetic testing environment, Intel has observed that some processor, chipset, and motherboard configurations may experience reduced Front Side Bus (FSB) voltage margin during some certain die-to-die data transfers. This combination of configurations and data transfers is rare. This lower voltage margin could lead to FSB data bit errors, which can lead to unpredictable system behavior.

Implication: When this erratum occurs, it leads to FSB marginality in the system during processor die-to-die transactions, which can lead to unpredictable system behavior. Intel has not observed this erratum with any commercially available software. Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.


Fixed in C1.

I'd say, pretty good chance this errata can be triggered in Linpack 64b, though i have not tested it myself.