Unleashing the Bear(lake): Changing "strap" on the fly

[xwoodoo]

Nice work Stilt. Still could you tell us what is the adress from mchbar which has to be changed in order to change the straps ?

[Xtreme Addict]

Amazing job!

[The Stilt]

As far as I know , the strap register is located in FED14C00h register bit 2/1/0 ... And the bit define is 010 = 800 MT/s , 000 = 1066 MT/s , 100 = 1333 MT/s ... And it's not possible to change strap define unless you have a system power off because the strap register is latched only once when the chipset power up in the first time , any system reset will not reset or relatch the strap register ... That's why everytime I change the strap setting , the P5K board shut it down and then power up again to make the new strap working ... If any other register can change the performance , it may be something else , but not the chipset strap setting at all ... Stilt , can u told us which register and what setting to change the performance level ?

Yes, address MemoryBaseAddress + C00h is R/O on P35/G33/G31.
This offset however is not the "strap" I am changing.

I don´t think this register has anything to do with the actual strap, since it just holds some FSEL (selected FSB; 533FSB, 800FSB, 1066FSB, 1333FSB) and divider information.

When the system is booted at 266FSB this register has a certain value corresponding (1066FSB FSEL). When the system is booted with 333FSB this register has a certain value corresponding (1333FSB FSEL).

However there is no difference in clock to clock performance between these different values.

Yes, I am not sure at all that this is the "strap" that I am changing.
Actually as far as I know the "strap" (as we call it) is just a internal chipset latency or set of latencies that can be tighten or loosen
in order to get additional performance or overclockability.

But since this tweak has so dramatic effect to the memory latency (at 570FSB from Level 10 to Level 5 = 10ns) it has probably something to with the "strap".

And no. I will not send this tweak to anyone but Felix.
Not because I´m an a**hole, but because on Asus boards certain tasks has to be completed before these registers are accessible.
Thats why it is better that Felix adds this feature to Memset, so it can be changed like any of dram timings.

[dinos22]

so HOW do you actually change it buddy

this is incredible and just what we've wanted

Gary mentioned the same thing the other day >> he was working with Asus on the same thing to get it implemented though bios



good on you man

[Warboy]

so HOW do you actually change it buddy

this is incredible and just what we've wanted

Gary mentioned the same thing the other day >> he was working with Asus on the same thing to get it implemented though bios



good on you man

I wish to know this too.

[xwoodoo]

Well,it seems that we have to wait for a new version of MemSet then.Rumours say that Gigabyte are working on a new bios with this so called "strap change" possible.

[wtz54321]

Yes, address MemoryBaseAddress + C00h is R/O on P35/G33/G31.
This offset however is not the "strap" I am changing.

I don´t think this register has anything to do with the actual strap, since it just holds some FSEL (selected FSB; 533FSB, 800FSB, 1066FSB, 1333FSB) and divider information.

When the system is booted at 266FSB this register has a certain value corresponding (1066FSB FSEL). When the system is booted with 333FSB this register has a certain value corresponding (1333FSB FSEL).

However there is no difference in clock to clock performance between these different values.

Yes, I am not sure at all that this is the "strap" that I am changing.
Actually as far as I know the "strap" (as we call it) is just a internal chipset latency or set of latencies that can be tighten or loosen
in order to get additional performance or overclockability.

But since this tweak has so dramatic effect to the memory latency (at 570FSB from Level 10 to Level 5 = 10ns) it has probably something to with the "strap".

And no. I will not send this tweak to anyone but Felix.
Not because I´m an a**hole, but because on Asus boards certain tasks has to be completed before these registers are accessible.
Thats why it is better that Felix adds this feature to Memset, so it can be changed like any of dram timings.

You mean how to unlock the MCHBAR register which is hidden by ASUS ? Yes , I know how to use WPCREDIT tool to unlock it and make it accessable by MCHBAREDIT tool , so is that possible to send it to me via PM ? Or just told me which MCHBAR register offset to test ? Will it be FED14030h to FED14047h ? I am so excited and can't wait to test it in my new P5K Deluxe board

[eva2000]

so HOW do you actually change it buddy

this is incredible and just what we've wanted

Gary mentioned the same thing the other day >> he was working with Asus on the same thing to get it implemented though bios



good on you man

maybe ?



but i prefer to wait for the bios update

[426hemi]

awesome! can't wait to dl it

[yotomeczek]

...
Thats why it is better that Felix adds this feature to Memset, so it can be changed like any of dram timings.

Maybe the quick how-to (for dumies ) with memset 3.3 ??

[Hutch]

Does it work for P965 also?

[Tony]

Been pushing to get this this table added to bios for a while now, issue is Asus regarded this as an internal tweak that made their boards clock higher than the rest, issue is its in the open and should force many to just add the options in bios.

I just got back from Taiwan and had lengthy discussion with Intel about chipset tweaking...there will be a lot more than this released soon....trust me

[eva2000]

Been pushing to get this this table added to bios for a while now, issue is Asus regarded this as an internal tweak that made their boards clock higher than the rest, issue is its in the open and should force many to just add the options in bios.

I just got back from Taiwan and had lengthy discussion with Intel about chipset tweaking...there will be a lot more than this released soon....trust me

didn't Intel say their own branded future boards will have alot of bios options for use overclockers this time round ?

[Tutti-frutti]

Hmm, I wonder if the "system performance" option (normal, turbo etc) in the Gigabyte bios has something to do with the strap settings.

edit: I looked in the bios of my P35-DS3P, but the option is gone in bios F3. It was available in bios F4.

edit2: Okay, flashed the P35-DS3P with the F5B bios. I was talking about this option:

[Warboy]

Hmm, I wonder if the "system performance" option (normal, turbo etc) in the Gigabyte bios has something to do with the strap settings.

edit: I looked in the bios of my P35-DS3P, but the option is gone in bios F3. It was available in bios F4.

edit2: Okay, flashed the P35-DS3P with the F5B bios. I was talking about this option:

Thats possible a good question :P

[xwoodoo]

can you please tell me where did ya get the f5b bios for p35-ds3?i wonder if there is one for my p35-dq6.Thanks a lot.

[kiwi]

Hmm, I wonder if the "system performance" option (normal, turbo etc) in the Gigabyte bios has something to do with the strap settings.

No, there is no difference between these 3 options But DS3R has a strap change at 417

[Tutti-frutti]

can you please tell me where did ya get the f5b bios for p35-ds3?i wonder if there is one for my p35-dq6.Thanks a lot.

psst...

[Brama]

psst...

I will try this night as I have a lot of troubles to find stability even at default settings with my DQ6 and Corsair Dominator 8500 C5

[XtremeTiramisu]

I'm still trying to figure out what's the sweetspot using 1:1 ratio for P5K-Dlx.

Stilt and Eva2000 tested 5:6 and 4:5 respectively at FSB500+ and I'd like to know where is the exact sweetspot using 1:1 ratio at high FSB before & after the strap change to acheive highest possible memory bandwidth.

I just bought the Asus P5K-Dlx a couple days ago but I'm still waiting for the Ballistix 8500 to come in. I was able to overclock my E6700 up to 3730mhz (FSB466 x 8) at 1.48v.

I'm aiming for higher FSB533 with the P5K-Dlx and keep the same clock at 3730, x7 multi, and use 1:1 ratio.

According to Eva's strap change finding at FSB500, I'm wondering how high of the FSB will I have to raise to regain the performance before the strap changes at 499??

Could FSB533 possibly be high enough to get the same amount of MB at 499?

May I please ask all P5K-Dlx owners to test the MB changes using 1:1 ratio (FSB499 ~ FSB500+) ??

TIA

[bingo13]

didn't Intel say their own branded future boards will have alot of bios options for use overclockers this time round ?

The BIOS version of Bonetrail I saw looked like Oskar on meth while coding...

[eva2000]

The BIOS version of Bonetrail I saw looked like Oskar on meth while coding...

but is that a good or bad thing ? LOL

[GazC]

Hmm, I wonder if the "system performance" option (normal, turbo etc) in the Gigabyte bios has something to do with the strap settings.

edit: I looked in the bios of my P35-DS3P, but the option is gone in bios F3. It was available in bios F4.

edit2: Okay, flashed the P35-DS3P with the F5B bios. I was talking about this option:

<snip>

Thats possible a good question :P

I'm not sure if that option is working properly on the P35-DQ6 at least. Standard seems to give me higher bandwidth than either of the other settings.

[erwinz]

very nice.. thanks for sharing..

[ziddey]

any input on this with the cheap ds3r board? I'm looking to go p35 and get <50ns 9000mb+ running 500 1:1. figure it'd definitely need advancement in strap to achieve this. planned for gigabyte? not seen any mbench results for users of ds3r.

gigabyte looking attractive since it's the only board seemingly to still have legacy support for serial/parallel. thank god for that.