Unleashing the Bear(lake): Changing "strap" on the fly

[The Stilt]

As far as I know , the strap register is located in FED14C00h register bit 2/1/0 ... And the bit define is 010 = 800 MT/s , 000 = 1066 MT/s , 100 = 1333 MT/s ... And it's not possible to change strap define unless you have a system power off because the strap register is latched only once when the chipset power up in the first time , any system reset will not reset or relatch the strap register ... That's why everytime I change the strap setting , the P5K board shut it down and then power up again to make the new strap working ... If any other register can change the performance , it may be something else , but not the chipset strap setting at all ... Stilt , can u told us which register and what setting to change the performance level ?

Yes, address MemoryBaseAddress + C00h is R/O on P35/G33/G31.
This offset however is not the "strap" I am changing.

I don´t think this register has anything to do with the actual strap, since it just holds some FSEL (selected FSB; 533FSB, 800FSB, 1066FSB, 1333FSB) and divider information.

When the system is booted at 266FSB this register has a certain value corresponding (1066FSB FSEL). When the system is booted with 333FSB this register has a certain value corresponding (1333FSB FSEL).

However there is no difference in clock to clock performance between these different values.

Yes, I am not sure at all that this is the "strap" that I am changing.
Actually as far as I know the "strap" (as we call it) is just a internal chipset latency or set of latencies that can be tighten or loosen
in order to get additional performance or overclockability.

But since this tweak has so dramatic effect to the memory latency (at 570FSB from Level 10 to Level 5 = 10ns) it has probably something to with the "strap".

And no. I will not send this tweak to anyone but Felix.
Not because I´m an a**hole, but because on Asus boards certain tasks has to be completed before these registers are accessible.
Thats why it is better that Felix adds this feature to Memset, so it can be changed like any of dram timings.